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Make the x86 asm flavor part of the subtarget info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30146 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -23,28 +23,11 @@
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#include "llvm/Type.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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enum AsmWriterFlavorTy { att, intel };
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Statistic<> llvm::EmittedInsts("asm-printer",
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"Number of machine instrs printed");
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cl::opt<AsmWriterFlavorTy>
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AsmWriterFlavor("x86-asm-syntax",
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cl::desc("Choose style of code to emit from X86 backend:"),
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cl::values(
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clEnumVal(att, " Emit AT&T-style assembly"),
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clEnumVal(intel, " Emit Intel-style assembly"),
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clEnumValEnd),
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#ifdef _MSC_VER
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cl::init(intel)
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#else
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cl::init(att)
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#endif
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);
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X86TargetAsmInfo::X86TargetAsmInfo(X86TargetMachine &TM) {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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@ -97,7 +80,7 @@ X86TargetAsmInfo::X86TargetAsmInfo(X86TargetMachine &TM) {
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default: break;
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}
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if (AsmWriterFlavor == intel) {
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if (Subtarget->isFlavorIntel()) {
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GlobalPrefix = "_";
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CommentString = ";";
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@ -271,12 +254,12 @@ bool X86SharedAsmPrinter::doFinalization(Module &M) {
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///
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FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,
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X86TargetMachine &tm) {
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const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
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TargetAsmInfo *TAI = new X86TargetAsmInfo(tm);
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switch (AsmWriterFlavor) {
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default:
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assert(0 && "Unknown asm flavor!");
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case intel: return new X86IntelAsmPrinter(o, tm, TAI);
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case att: return new X86ATTAsmPrinter(o, tm, TAI);
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if (Subtarget->isFlavorIntel()) {
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return new X86IntelAsmPrinter(o, tm, TAI);
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} else {
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return new X86ATTAsmPrinter(o, tm, TAI);
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}
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}
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@ -13,9 +13,24 @@
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#include "X86Subtarget.h"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "X86GenSubtarget.inc"
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using namespace llvm;
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cl::opt<X86Subtarget::AsmWriterFlavorTy>
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AsmWriterFlavor("x86-asm-syntax",
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cl::desc("Choose style of code to emit from X86 backend:"),
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cl::values(
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clEnumValN(X86Subtarget::att, "att", " Emit AT&T-style assembly"),
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clEnumValN(X86Subtarget::intel, "intel", " Emit Intel-style assembly"),
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clEnumValEnd),
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#ifdef _MSC_VER
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cl::init(X86Subtarget::intel)
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#else
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cl::init(X86Subtarget::att)
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#endif
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);
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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@ -151,6 +166,7 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS) {
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MinRepStrSizeThreshold = 128;
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X86SSELevel = NoMMXSSE;
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X863DNowLevel = NoThreeDNow;
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AsmFlavor = AsmWriterFlavor;
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Is64Bit = false;
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// Determine default and user specified characteristics
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@ -22,6 +22,11 @@ namespace llvm {
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class Module;
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class X86Subtarget : public TargetSubtarget {
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public:
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enum AsmWriterFlavorTy {
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att, intel
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};
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protected:
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enum X86SSEEnum {
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NoMMXSSE, MMX, SSE1, SSE2, SSE3
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@ -31,12 +36,15 @@ protected:
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NoThreeDNow, ThreeDNow, ThreeDNowA
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};
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/// AsmFlavor - Which x86 asm dialect to use.
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AsmWriterFlavorTy AsmFlavor;
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/// X86SSELevel - MMX, SSE1, SSE2, SSE3, or none supported.
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X86SSEEnum X86SSELevel;
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/// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
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X863DNowEnum X863DNowLevel;
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/// Is64Bit - True if the processor supports Em64T.
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bool Is64Bit;
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@ -80,6 +88,9 @@ public:
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bool hasSSE3() const { return X86SSELevel >= SSE3; }
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bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool isFlavorAtt() const { return AsmFlavor == att; }
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bool isFlavorIntel() const { return AsmFlavor == intel; }
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bool isTargetDarwin() const { return TargetType == isDarwin; }
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bool isTargetELF() const { return TargetType == isELF; }
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