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[SimplifyCFG] Be even more conservative in SinkThenElseCodeToEnd
This should *actually* fix PR30244. This cranks up the workaround for PR30188 so that we never sink loads or stores of allocas. The idea is that these should be removed by SROA/Mem2Reg, and any movement of them may well confuse SROA or just cause unwanted code churn. It's not ideal that the midend should be crippled like this, but that unwanted churn can really cause significant regressions in important workloads (tsan). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281162 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1428,6 +1428,25 @@ static bool canSinkInstructions(
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if (I0->getOperand(OI)->getType()->isTokenTy())
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// Don't touch any operand of token type.
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return false;
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// Because SROA can't handle speculating stores of selects, try not
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// to sink loads or stores of allocas when we'd have to create a PHI for
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// the address operand. Also, because it is likely that loads or stores
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// of allocas will disappear when Mem2Reg/SROA is run, don't sink them.
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// This can cause code churn which can have unintended consequences down
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// the line - see https://llvm.org/bugs/show_bug.cgi?id=30244.
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// FIXME: This is a workaround for a deficiency in SROA - see
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// https://llvm.org/bugs/show_bug.cgi?id=30188
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if (OI == 1 && isa<StoreInst>(I0) &&
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any_of(Insts, [](const Instruction *I) {
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return isa<AllocaInst>(I->getOperand(1));
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}))
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return false;
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if (OI == 0 && isa<LoadInst>(I0) && any_of(Insts, [](const Instruction *I) {
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return isa<AllocaInst>(I->getOperand(0));
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}))
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return false;
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auto SameAsI0 = [&I0, OI](const Instruction *I) {
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assert(I->getNumOperands() == I0->getNumOperands());
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return I->getOperand(OI) == I0->getOperand(OI);
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@ -1441,21 +1460,6 @@ static bool canSinkInstructions(
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// FIXME: if the call was *already* indirect, we should do this.
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return false;
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}
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// Because SROA can't handle speculating stores of selects, try not
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// to sink loads or stores of allocas when we'd have to create a PHI for
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// the address operand.
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// FIXME: This is a workaround for a deficiency in SROA - see
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// https://llvm.org/bugs/show_bug.cgi?id=30188
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if (OI == 1 && isa<StoreInst>(I0) &&
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any_of(Insts, [](const Instruction *I) {
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return isa<AllocaInst>(I->getOperand(1));
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}))
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return false;
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if (OI == 0 && isa<LoadInst>(I0) &&
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any_of(Insts, [](const Instruction *I) {
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return isa<AllocaInst>(I->getOperand(0));
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}))
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return false;
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for (auto *I : Insts)
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PHIOperands[I].push_back(I->getOperand(OI));
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}
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@ -1,4 +1,4 @@
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; RUN: opt < %s -simplifycfg -S | FileCheck %s
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; RUN: opt < %s -mem2reg -simplifycfg -S | FileCheck %s
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define i32 @test(i32 %x) {
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; CHECK-LABEL: @test
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@ -23,7 +23,7 @@ if.else:
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if.end:
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; CHECK-LABEL: if.end:
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; CHECK: {{%.*}} = phi i32 [ [[ASM2]], %if.else ], [ [[ASM1]], %if.then ]
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; CHECK: {{%.*}} = phi i32 [ [[ASM1]], %if.then ], [ [[ASM2]], %if.else ]
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%tmp3 = load i32, i32* %y, align 4
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ret i32 %tmp3
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}
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@ -669,24 +669,35 @@ declare void @g()
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; CHECK-LABEL: test_pr30292
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; CHECK: phi i32 [ 0, %entry ], [ %add1, %succ ], [ %add2, %two ]
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define void @test_pr30244(i1 %cond, i1 %cond2, i32 %a, i32 %b) {
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define zeroext i1 @test_pr30244(i1 zeroext %flag, i1 zeroext %flag2, i32 %blksA, i32 %blksB, i32 %nblks) {
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entry:
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%add1 = add i32 %a, 1
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br label %succ
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%p = alloca i8
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br i1 %flag, label %if.then, label %if.else
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one:
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br i1 %cond, label %two, label %succ
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if.then:
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%cmp = icmp uge i32 %blksA, %nblks
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%frombool1 = zext i1 %cmp to i8
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store i8 %frombool1, i8* %p
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br label %if.end
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two:
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call void @g()
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%add2 = add i32 %a, 1
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br label %succ
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if.else:
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br i1 %flag2, label %if.then2, label %if.end
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succ:
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%p = phi i32 [ 0, %entry ], [ %add1, %one ], [ %add2, %two ]
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br label %one
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if.then2:
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%add = add i32 %nblks, %blksB
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%cmp2 = icmp ule i32 %add, %blksA
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%frombool3 = zext i1 %cmp2 to i8
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store i8 %frombool3, i8* %p
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br label %if.end
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if.end:
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ret i1 true
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}
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; CHECK-LABEL: @test_pr30244
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; CHECK: store
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; CHECK: store
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; CHECK: !0 = !{!1, !1, i64 0}
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; CHECK: !1 = !{!"float", !2}
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