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Thumb2 assembly parsing and encoding for SRS.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-09-16 18:25:22 +00:00
parent dea8412784
commit 05ec8f7ac9
2 changed files with 48 additions and 20 deletions
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38
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3300,32 +3300,30 @@ def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
let Inst{19-16} = opt; let Inst{19-16} = opt;
} }
class T2SRS<bits<12> op31_20, class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
dag oops, dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> { : T2I<oops, iops, itin, opc, asm, pattern> {
let Inst{31-20} = op31_20{11-0};
bits<5> mode; bits<5> mode;
let Inst{31-25} = 0b1110100;
let Inst{24-23} = Op;
let Inst{22} = 0;
let Inst{21} = W;
let Inst{20-16} = 0b01101;
let Inst{15-5} = 0b11000000000;
let Inst{4-0} = mode{4-0}; let Inst{4-0} = mode{4-0};
} }
// Store Return State is a system instruction -- for disassembly only // Store Return State is a system instruction.
def t2SRSDBW : T2SRS<0b111010000010, def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode", "srsdb", "\tsp!, $mode", []>;
[/* For disassembly only; pattern left blank */]>; def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
def t2SRSDB : T2SRS<0b111010000000, "srsdb","\tsp, $mode", []>;
(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode", def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
[/* For disassembly only; pattern left blank */]>; "srsia","\tsp!, $mode", []>;
def t2SRSIAW : T2SRS<0b111010011010, def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode", "srsia","\tsp, $mode", []>;
[/* For disassembly only; pattern left blank */]>;
def t2SRSIA : T2SRS<0b111010011000,
(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
[/* For disassembly only; pattern left blank */]>;
// Return From Exception is a system instruction -- for disassembly only
// Return From Exception is a system instruction.
class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> { : T2I<oops, iops, itin, opc, asm, pattern> {

30
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -2018,6 +2018,36 @@ _func:
@ CHECK: smusdxne r7, r4, r3 @ encoding: [0x44,0xfb,0x13,0xf7] @ CHECK: smusdxne r7, r4, r3 @ encoding: [0x44,0xfb,0x13,0xf7]
@------------------------------------------------------------------------------
@ SRS
@------------------------------------------------------------------------------
srsdb sp, #1
srsia sp, #0
srsdb sp!, #19
srsia sp!, #2
srsea sp, #10
srsfd sp, #9
srsea sp!, #5
srsfd sp!, #5
srs sp, #5
srs sp!, #5
@ CHECK: srsdb sp, #1 @ encoding: [0x0d,0xe8,0x01,0xc0]
@ CHECK: srsia sp, #0 @ encoding: [0x8d,0xe9,0x00,0xc0]
@ CHECK: srsdb sp!, #19 @ encoding: [0x2d,0xe8,0x13,0xc0]
@ CHECK: srsia sp!, #2 @ encoding: [0xad,0xe9,0x02,0xc0]
@ CHECK: srsdb sp, #10 @ encoding: [0x0d,0xe8,0x0a,0xc0]
@ CHECK: srsia sp, #9 @ encoding: [0x8d,0xe9,0x09,0xc0]
@ CHECK: srsdb sp!, #5 @ encoding: [0x2d,0xe8,0x05,0xc0]
@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0]
@ CHECK: srsia sp, #5 @ encoding: [0x8d,0xe9,0x05,0xc0]
@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
@ SUB (register) @ SUB (register)
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------