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Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109198 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2729,15 +2729,15 @@ def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
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// Insert
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let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
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def PINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
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defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
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def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
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"vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in
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defm VPINSRW : sse2_pinsrw, TB, OpSize;
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defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
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} // ExeDomain = SSEPackedInt
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@ -3026,7 +3026,7 @@ def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
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// xr = XMM register
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// xm = mem64
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let isAsmParserOnly = 1 in
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let isAsmParserOnly = 1, Predicates = [HasAVX] in
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def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
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def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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@ -5213,9 +5213,11 @@ def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
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[]>, VEX_4V;
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// Zero All YMM registers
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def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L;
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def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L,
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Requires<[HasAVX]>;
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// Zero Upper bits of YMM registers
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def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX;
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def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX,
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Requires<[HasAVX]>;
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} // isAsmParserOnly
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