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Add operand encoding bits for SMC and SVC in ARM mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-13 22:38:23 +00:00
parent 832859d062
commit 06ef444e5c
1 changed files with 7 additions and 3 deletions
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10
lib/Target/ARM/ARMInstrInfo.td
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@ -1295,14 +1295,18 @@ def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
// Secure Monitor Call is a system instruction -- for disassembly only
def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
[/* For disassembly only; pattern left blank */]> {
let Inst{23-20} = 0b0110;
let Inst{7-4} = 0b0111;
bits<4> opt;
let Inst{23-4} = 0b01100000000000000111;
let Inst{3-0} = opt;
}
// Supervisor Call (Software Interrupt) -- for disassembly only
let isCall = 1 in {
def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
[/* For disassembly only; pattern left blank */]>;
[/* For disassembly only; pattern left blank */]> {
bits<24> svc;
let Inst{23-0} = svc;
}
}
// Store Return State is a system instruction -- for disassembly only