From 071367dcb625d012481007b2ad0bd9c05c7fa44e Mon Sep 17 00:00:00 2001 From: Nekotekina Date: Tue, 30 Jan 2018 00:50:12 +0300 Subject: [PATCH] X86: combine inversion of VPTERNLOG --- lib/Target/X86/X86ISelLowering.cpp | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index eb8391822b3..9a2d72c8a70 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -41724,6 +41724,10 @@ static SDValue foldXor1SetCC(SDNode *N, SelectionDAG &DAG) { static SDValue combineXor(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + EVT VT = N->getValueType(0); + // If this is SSE1 only convert to FXOR to avoid scalarization. if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && N->getValueType(0) == MVT::v4i32) { @@ -41748,7 +41752,23 @@ static SDValue combineXor(SDNode *N, SelectionDAG &DAG, if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget)) return FPLogic; - return combineFneg(N, DAG, Subtarget); + if (isFNEG(DAG, N)) + return combineFneg(N, DAG, Subtarget); + + if (ISD::isBuildVectorAllOnes(N0.getNode())) + std::swap(N0, N1); + + if (Subtarget.hasAVX512() && N0.getOpcode() == X86ISD::VPTERNLOG && + ISD::isBuildVectorAllOnes(N1.getNode())) { + // Invert ternary logic result by inverting its truth table. + SDLoc DL(N); + uint64_t C = cast(N0.getOperand(3))->getZExtValue() ^ 0xff; + SDValue R = DAG.getNode(X86ISD::VPTERNLOG, DL, N0.getValueType(), + N0.getOperand(0), N0.getOperand(1), + N0.getOperand(2), DAG.getConstant(C, DL, MVT::i8)); + return DAG.getBitcast(VT, R); + } + return SDValue(); } static SDValue combineBEXTR(SDNode *N, SelectionDAG &DAG,