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LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG when it is a question of expanding or promoting the result type: for example, if extracting an i64 from a <2 x i64>, when i64 needs expanding, it bitcasts the vector to <4 x i32>, extracts the appropriate two i32's, and uses those for the Lo and Hi parts. Likewise, when extracting an i16 from a <4 x i16>, and i16 needs promoting, it bitcasts the vector to <2 x i32>, extracts the appropriate i32, twiddles the bits if necessary, and uses that as the promoted value. This puts more pressure on bitcast legalization, and I've added the appropriate cases. They needed to be added anyway since users can generate such bitcasts too if they want to. Also, when considering various cases (Legal, Promote, Expand, Scalarize, Split) it is a pain that expand can correspond to Expand, Scalarize or Split, so I've changed the LegalizeTypes enum so it lists those different cases - now Expand only means splitting a scalar in two. The code produced is the same as by LegalizeDAG for all relevant testcases, except for 2007-10-31-extractelement-i64.ll, where the code seems to have improved (see below; can an expert please tell me if it is better or not). Before < vs after >. < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 28(%esp) < movl (%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 28(%esp) < movl 8(%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 16(%esp), %eax < movl %eax, 48(%esp) < movl 20(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 60(%esp) < movl (%esp), %eax < movl %eax, 56(%esp) --- > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 24(%esp), %eax < movl %eax, 48(%esp) < movl 28(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 60(%esp) < movl 8(%esp), %eax < movl %eax, 56(%esp) --- > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands
parent
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commit
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@ -68,25 +68,26 @@ void DAGTypeLegalizer::run() {
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unsigned NumResults = N->getNumValues();
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do {
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MVT::ValueType ResultVT = N->getValueType(i);
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LegalizeAction Action = getTypeAction(ResultVT);
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if (Action == Promote) {
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switch (getTypeAction(ResultVT)) {
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default:
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assert(false && "Unknown action!");
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case Legal:
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break;
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case Promote:
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PromoteResult(N, i);
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goto NodeDone;
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} else if (Action == Expand) {
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// Expand can mean 1) split integer in half 2) scalarize single-element
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// vector 3) split vector in half.
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if (!MVT::isVector(ResultVT))
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ExpandResult(N, i);
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else if (MVT::getVectorNumElements(ResultVT) == 1)
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ScalarizeResult(N, i); // Scalarize the single-element vector.
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else
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SplitResult(N, i); // Split the vector in half.
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case Expand:
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ExpandResult(N, i);
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goto NodeDone;
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case Scalarize:
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ScalarizeResult(N, i);
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goto NodeDone;
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case Split:
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SplitResult(N, i);
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goto NodeDone;
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} else {
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assert(Action == Legal && "Unknown action!");
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}
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} while (++i < NumResults);
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// Scan the operand list for the node, handling any nodes with operands that
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// are illegal.
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{
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@ -94,25 +95,25 @@ void DAGTypeLegalizer::run() {
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bool NeedsRevisit = false;
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for (i = 0; i != NumOperands; ++i) {
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MVT::ValueType OpVT = N->getOperand(i).getValueType();
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LegalizeAction Action = getTypeAction(OpVT);
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if (Action == Promote) {
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switch (getTypeAction(OpVT)) {
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default:
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assert(false && "Unknown action!");
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case Legal:
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continue;
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case Promote:
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NeedsRevisit = PromoteOperand(N, i);
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break;
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} else if (Action == Expand) {
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// Expand can mean 1) split integer in half 2) scalarize single-element
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// vector 3) split vector in half.
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if (!MVT::isVector(OpVT)) {
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NeedsRevisit = ExpandOperand(N, i);
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} else if (MVT::getVectorNumElements(OpVT) == 1) {
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// Scalarize the single-element vector.
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NeedsRevisit = ScalarizeOperand(N, i);
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} else {
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NeedsRevisit = SplitOperand(N, i); // Split the vector in half.
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}
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case Expand:
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NeedsRevisit = ExpandOperand(N, i);
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break;
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case Scalarize:
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NeedsRevisit = ScalarizeOperand(N, i);
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break;
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case Split:
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NeedsRevisit = SplitOperand(N, i);
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break;
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} else {
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assert(Action == Legal && "Unknown action!");
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}
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break;
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}
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// If the node needs revisiting, don't add all users to the worklist etc.
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@ -432,7 +433,7 @@ SDOperand DAGTypeLegalizer::HandleMemIntrinsic(SDNode *N) {
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case Legal: break;
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case Promote: Op2 = GetPromotedOp(Op2); break;
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}
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// The length could have any action required.
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SDOperand Length = N->getOperand(3);
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switch (getTypeAction(Length.getValueType())) {
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@ -444,21 +445,21 @@ SDOperand DAGTypeLegalizer::HandleMemIntrinsic(SDNode *N) {
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GetExpandedOp(Length, Length, Dummy);
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break;
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}
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SDOperand Align = N->getOperand(4);
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switch (getTypeAction(Align.getValueType())) {
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default: assert(0 && "Unknown action for memop operand");
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case Legal: break;
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case Promote: Align = GetPromotedZExtOp(Align); break;
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}
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SDOperand AlwaysInline = N->getOperand(5);
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switch (getTypeAction(AlwaysInline.getValueType())) {
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default: assert(0 && "Unknown action for memop operand");
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case Legal: break;
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case Promote: AlwaysInline = GetPromotedZExtOp(AlwaysInline); break;
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}
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SDOperand Ops[] = { Chain, Ptr, Op2, Length, Align, AlwaysInline };
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return DAG.UpdateNodeOperands(SDOperand(N, 0), Ops, 6);
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}
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@ -61,27 +61,46 @@ private:
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enum LegalizeAction {
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Legal, // The target natively supports this type.
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Promote, // This type should be executed in a larger type.
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Expand // This type should be split into two types of half the size.
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Expand, // This type should be split into two types of half the size.
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Scalarize, // Replace this one-element vector type with its element type.
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Split // This vector type should be split into smaller vectors.
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};
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/// ValueTypeActions - This is a bitvector that contains two bits for each
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/// simple value type, where the two bits correspond to the LegalizeAction
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/// enum. This can be queried with "getTypeAction(VT)".
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/// enum from TargetLowering. This can be queried with "getTypeAction(VT)".
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TargetLowering::ValueTypeActionImpl ValueTypeActions;
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/// getTypeAction - Return how we should legalize values of this type, either
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/// it is already legal or we need to expand it into multiple registers of
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/// smaller integer type, or we need to promote it to a larger type.
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/// it is already legal, or we need to promote it to a larger integer type, or
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/// we need to expand it into multiple registers of a smaller integer type, or
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/// we need to scalarize a one-element vector type into the element type, or
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/// we need to split a vector type into smaller vector types.
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LegalizeAction getTypeAction(MVT::ValueType VT) const {
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return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
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switch (ValueTypeActions.getTypeAction(VT)) {
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default:
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assert(false && "Unknown legalize action!");
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case TargetLowering::Legal:
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return Legal;
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case TargetLowering::Promote:
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return Promote;
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case TargetLowering::Expand:
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// Expand can mean 1) split integer in half 2) scalarize single-element
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// vector 3) split vector in two.
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if (!MVT::isVector(VT))
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return Expand;
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else if (MVT::getVectorNumElements(VT) == 1)
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return Scalarize;
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else
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return Split;
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}
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}
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/// isTypeLegal - Return true if this type is legal on this target.
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///
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bool isTypeLegal(MVT::ValueType VT) const {
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return getTypeAction(VT) == Legal;
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return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal;
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}
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/// PromotedNodes - For nodes that are below legal width, this map indicates
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/// what promoted value to use.
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DenseMap<SDOperand, SDOperand> PromotedNodes;
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@ -159,11 +178,13 @@ private:
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// Result Promotion.
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void PromoteResult(SDNode *N, unsigned ResNo);
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SDOperand PromoteResult_BIT_CONVERT(SDNode *N);
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SDOperand PromoteResult_BUILD_PAIR(SDNode *N);
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SDOperand PromoteResult_Constant(SDNode *N);
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SDOperand PromoteResult_CTLZ(SDNode *N);
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SDOperand PromoteResult_CTPOP(SDNode *N);
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SDOperand PromoteResult_CTTZ(SDNode *N);
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SDOperand PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N);
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SDOperand PromoteResult_FP_ROUND(SDNode *N);
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SDOperand PromoteResult_FP_TO_XINT(SDNode *N);
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SDOperand PromoteResult_INT_EXTEND(SDNode *N);
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@ -219,6 +240,7 @@ private:
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void ExpandResult_CTLZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_CTPOP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_CTTZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_MERGE_VALUES(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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@ -283,6 +305,7 @@ private:
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// Operand Vector Scalarization: <1 x ty> -> ty.
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bool ScalarizeOperand(SDNode *N, unsigned OpNo);
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SDOperand ScalarizeOp_BIT_CONVERT(SDNode *N);
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SDOperand ScalarizeOp_EXTRACT_VECTOR_ELT(SDNode *N);
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SDOperand ScalarizeOp_STORE(StoreSDNode *N, unsigned OpNo);
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@ -313,7 +336,9 @@ private:
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// Operand Vector Scalarization: <128 x ty> -> 2 x <64 x ty>.
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bool SplitOperand(SDNode *N, unsigned OpNo);
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SDOperand SplitOp_BIT_CONVERT(SDNode *N);
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SDOperand SplitOp_EXTRACT_SUBVECTOR(SDNode *N);
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SDOperand SplitOp_EXTRACT_VECTOR_ELT(SDNode *N);
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SDOperand SplitOp_RET(SDNode *N, unsigned OpNo);
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SDOperand SplitOp_STORE(StoreSDNode *N, unsigned OpNo);
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SDOperand SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
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@ -86,6 +86,10 @@ void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
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case ISD::CTLZ: ExpandResult_CTLZ(N, Lo, Hi); break;
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case ISD::CTPOP: ExpandResult_CTPOP(N, Lo, Hi); break;
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case ISD::CTTZ: ExpandResult_CTTZ(N, Lo, Hi); break;
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case ISD::EXTRACT_VECTOR_ELT:
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ExpandResult_EXTRACT_VECTOR_ELT(N, Lo, Hi);
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break;
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}
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// If Lo/Hi is null, the sub-method took care of registering results etc.
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@ -147,7 +151,7 @@ void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N,
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// For example, extension of an i48 to an i64. The operand type necessarily
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// promotes to the result type, so will end up being expanded too.
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assert(getTypeAction(Op.getValueType()) == Promote &&
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"Don't know how to expand this result!");
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"Only know how to promote this result!");
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SDOperand Res = GetPromotedOp(Op);
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assert(Res.getValueType() == N->getValueType(0) &&
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"Operand over promoted?");
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@ -168,7 +172,7 @@ void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N,
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// For example, extension of an i48 to an i64. The operand type necessarily
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// promotes to the result type, so will end up being expanded too.
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assert(getTypeAction(Op.getValueType()) == Promote &&
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"Don't know how to expand this result!");
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"Only know how to promote this result!");
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SDOperand Res = GetPromotedOp(Op);
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assert(Res.getValueType() == N->getValueType(0) &&
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"Operand over promoted?");
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@ -195,7 +199,7 @@ void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N,
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// For example, extension of an i48 to an i64. The operand type necessarily
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// promotes to the result type, so will end up being expanded too.
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assert(getTypeAction(Op.getValueType()) == Promote &&
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"Don't know how to expand this result!");
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"Only know how to promote this result!");
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SDOperand Res = GetPromotedOp(Op);
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assert(Res.getValueType() == N->getValueType(0) &&
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"Operand over promoted?");
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@ -239,6 +243,8 @@ void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N,
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void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// Lower the bit-convert to a store/load from the stack, then expand the load.
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// TODO: If the operand also needs expansion then this could be turned into
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// conversion of the expanded pieces. But there needs to be a testcase first!
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SDOperand Op = CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
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ExpandResult_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
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}
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@ -666,6 +672,41 @@ void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N,
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Hi = DAG.getConstant(0, NVT);
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}
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void DAGTypeLegalizer::ExpandResult_EXTRACT_VECTOR_ELT(SDNode *N,
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SDOperand &Lo,
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SDOperand &Hi) {
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SDOperand OldVec = N->getOperand(0);
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unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType());
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// Convert to a vector of the expanded element type, for example
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// <2 x i64> -> <4 x i32>.
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MVT::ValueType OldVT = N->getValueType(0);
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MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT);
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assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) &&
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"Do not know how to handle this expansion!");
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SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
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MVT::getVectorType(NewVT, 2 * OldElts),
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OldVec);
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// Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
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SDOperand Idx = N->getOperand(1);
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// Make sure the type of Idx is big enough to hold the new values.
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if (MVT::getSizeInBits(Idx.getValueType()) < 32)
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Idx = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Idx);
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Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx);
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Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, Idx);
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Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx,
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DAG.getConstant(1, Idx.getValueType()));
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Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, Idx);
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if (TLI.isBigEndian())
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std::swap(Lo, Hi);
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}
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/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
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/// and the shift amount is a constant 'Amt'. Expand the operation.
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void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
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@ -898,6 +939,28 @@ SDOperand DAGTypeLegalizer::ExpandOperand_TRUNCATE(SDNode *N) {
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}
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SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) {
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if (MVT::isVector(N->getValueType(0))) {
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// An illegal integer type is being converted to a legal vector type.
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// Make a two element vector out of the expanded parts and convert that
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// instead, but only if the new vector type is legal (otherwise there
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// is no point, and it might create expansion loops). For example, on
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// x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32.
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MVT::ValueType OVT = N->getOperand(0).getValueType();
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MVT::ValueType NVT = MVT::getVectorType(TLI.getTypeToTransformTo(OVT), 2);
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if (isTypeLegal(NVT)) {
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SDOperand Parts[2];
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GetExpandedOp(N->getOperand(0), Parts[0], Parts[1]);
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if (TLI.isBigEndian())
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std::swap(Parts[0], Parts[1]);
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SDOperand Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2);
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return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Vec);
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}
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}
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// Otherwise, store to a temporary and load out again as the new type.
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return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
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}
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@ -50,6 +50,7 @@ void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
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case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
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case ISD::LOAD: Result = PromoteResult_LOAD(cast<LoadSDNode>(N)); break;
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case ISD::BUILD_PAIR: Result = PromoteResult_BUILD_PAIR(N); break;
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case ISD::BIT_CONVERT: Result = PromoteResult_BIT_CONVERT(N); break;
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case ISD::AND:
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case ISD::OR:
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@ -74,8 +75,12 @@ void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
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case ISD::CTLZ: Result = PromoteResult_CTLZ(N); break;
|
||||
case ISD::CTPOP: Result = PromoteResult_CTPOP(N); break;
|
||||
case ISD::CTTZ: Result = PromoteResult_CTTZ(N); break;
|
||||
|
||||
case ISD::EXTRACT_VECTOR_ELT:
|
||||
Result = PromoteResult_EXTRACT_VECTOR_ELT(N);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
// If Result is null, the sub-method took care of registering the result.
|
||||
if (Result.Val)
|
||||
SetPromotedOp(SDOperand(N, ResNo), Result);
|
||||
@ -214,6 +219,65 @@ SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) {
|
||||
return DAG.getNode(ISD::OR, NVT, Lo, Hi);
|
||||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) {
|
||||
SDOperand InOp = N->getOperand(0);
|
||||
MVT::ValueType InVT = InOp.getValueType();
|
||||
MVT::ValueType NInVT = TLI.getTypeToTransformTo(InVT);
|
||||
MVT::ValueType OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
|
||||
|
||||
switch (getTypeAction(InVT)) {
|
||||
default:
|
||||
assert(false && "Unknown type action!");
|
||||
break;
|
||||
case Legal:
|
||||
break;
|
||||
case Promote:
|
||||
if (MVT::getSizeInBits(OutVT) == MVT::getSizeInBits(NInVT))
|
||||
// The input promotes to the same size. Convert the promoted value.
|
||||
return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedOp(InOp));
|
||||
break;
|
||||
case Expand:
|
||||
break;
|
||||
case Scalarize:
|
||||
// Convert the element to an integer and promote it by hand.
|
||||
InOp = DAG.getNode(ISD::BIT_CONVERT,
|
||||
MVT::getIntegerType(MVT::getSizeInBits(InVT)),
|
||||
GetScalarizedOp(InOp));
|
||||
InOp = DAG.getNode(ISD::ANY_EXTEND,
|
||||
MVT::getIntegerType(MVT::getSizeInBits(OutVT)), InOp);
|
||||
return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
|
||||
case Split:
|
||||
// For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
|
||||
// pieces of the input into integers and reassemble in the final type.
|
||||
SDOperand Lo, Hi;
|
||||
GetSplitOp(N->getOperand(0), Lo, Hi);
|
||||
|
||||
unsigned LoBits = MVT::getSizeInBits(Lo.getValueType());
|
||||
Lo = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(LoBits), Lo);
|
||||
|
||||
unsigned HiBits = MVT::getSizeInBits(Hi.getValueType());
|
||||
Hi = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(HiBits), Hi);
|
||||
|
||||
if (TLI.isBigEndian())
|
||||
std::swap(Lo, Hi);
|
||||
|
||||
MVT::ValueType TargetTy = MVT::getIntegerType(MVT::getSizeInBits(OutVT));
|
||||
Hi = DAG.getNode(ISD::ANY_EXTEND, TargetTy, Hi);
|
||||
Hi = DAG.getNode(ISD::SHL, TargetTy, Hi,
|
||||
DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
|
||||
TLI.getShiftAmountTy()));
|
||||
Lo = DAG.getNode(ISD::ZERO_EXTEND, TargetTy, Lo);
|
||||
|
||||
return DAG.getNode(ISD::BIT_CONVERT, OutVT,
|
||||
DAG.getNode(ISD::OR, TargetTy, Lo, Hi));
|
||||
}
|
||||
|
||||
// Otherwise, lower the bit-convert to a store/load from the stack, then
|
||||
// promote the load.
|
||||
SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
|
||||
return PromoteResult_LOAD(cast<LoadSDNode>(Op.Val));
|
||||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
|
||||
// The input may have strange things in the top bits of the registers, but
|
||||
// these operations don't care. They may have weird bits going out, but
|
||||
@ -315,6 +379,51 @@ SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) {
|
||||
return DAG.getNode(ISD::CTTZ, NVT, Op);
|
||||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) {
|
||||
MVT::ValueType OldVT = N->getValueType(0);
|
||||
SDOperand OldVec = N->getOperand(0);
|
||||
unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType());
|
||||
|
||||
if (OldElts == 1) {
|
||||
assert(!isTypeLegal(OldVec.getValueType()) &&
|
||||
"Legal one-element vector of a type needing promotion!");
|
||||
// It is tempting to follow GetScalarizedOp by a call to GetPromotedOp,
|
||||
// but this would be wrong because the scalarized value may not yet have
|
||||
// been processed.
|
||||
return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
|
||||
GetScalarizedOp(OldVec));
|
||||
}
|
||||
|
||||
// Convert to a vector half as long with an element type of twice the width,
|
||||
// for example <4 x i16> -> <2 x i32>.
|
||||
assert(!(OldElts & 1) && "Odd length vectors not supported!");
|
||||
MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
|
||||
assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
|
||||
|
||||
SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
|
||||
MVT::getVectorType(NewVT, OldElts / 2),
|
||||
OldVec);
|
||||
|
||||
// Extract the element at OldIdx / 2 from the new vector.
|
||||
SDOperand OldIdx = N->getOperand(1);
|
||||
SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
|
||||
DAG.getConstant(1, TLI.getShiftAmountTy()));
|
||||
SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
|
||||
|
||||
// Select the appropriate half of the element: Lo if OldIdx was even,
|
||||
// Hi if it was odd.
|
||||
SDOperand Lo = Elt;
|
||||
SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
|
||||
DAG.getConstant(MVT::getSizeInBits(OldVT),
|
||||
TLI.getShiftAmountTy()));
|
||||
if (TLI.isBigEndian())
|
||||
std::swap(Lo, Hi);
|
||||
|
||||
SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
|
||||
DAG.getConstant(1, TLI.getShiftAmountTy()));
|
||||
return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Operand Promotion
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -176,6 +176,9 @@ bool DAGTypeLegalizer::ScalarizeOperand(SDNode *N, unsigned OpNo) {
|
||||
assert(0 && "Do not know how to scalarize this operator's operand!");
|
||||
abort();
|
||||
|
||||
case ISD::BIT_CONVERT:
|
||||
Res = ScalarizeOp_BIT_CONVERT(N); break;
|
||||
|
||||
case ISD::EXTRACT_VECTOR_ELT:
|
||||
Res = ScalarizeOp_EXTRACT_VECTOR_ELT(N); break;
|
||||
|
||||
@ -204,6 +207,13 @@ bool DAGTypeLegalizer::ScalarizeOperand(SDNode *N, unsigned OpNo) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// ScalarizeOp_BIT_CONVERT - If the value to convert is a vector that needs
|
||||
/// to be scalarized, it must be <1 x ty>. Convert the element instead.
|
||||
SDOperand DAGTypeLegalizer::ScalarizeOp_BIT_CONVERT(SDNode *N) {
|
||||
SDOperand Elt = GetScalarizedOp(N->getOperand(0));
|
||||
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
|
||||
}
|
||||
|
||||
/// ScalarizeOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to be
|
||||
/// scalarized, it must be <1 x ty>, so just return the element, ignoring the
|
||||
/// index.
|
||||
|
||||
@ -172,7 +172,6 @@ void DAGTypeLegalizer::SplitRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
|
||||
else
|
||||
Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, ScalarOp,
|
||||
DAG.getConstant(Index - LoNumElts, TLI.getPointerTy()));
|
||||
|
||||
}
|
||||
|
||||
void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N,
|
||||
@ -253,22 +252,50 @@ void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N,
|
||||
SDOperand &Lo, SDOperand &Hi) {
|
||||
// We know the result is a vector. The input may be either a vector or a
|
||||
// scalar value.
|
||||
SDOperand InOp = N->getOperand(0);
|
||||
if (MVT::isVector(InOp.getValueType()) &&
|
||||
MVT::getVectorNumElements(InOp.getValueType()) != 1) {
|
||||
// If this is a vector, split the vector and convert each of the pieces now.
|
||||
GetSplitOp(InOp, Lo, Hi);
|
||||
|
||||
MVT::ValueType LoVT, HiVT;
|
||||
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
||||
MVT::ValueType LoVT, HiVT;
|
||||
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
||||
|
||||
SDOperand InOp = N->getOperand(0);
|
||||
MVT::ValueType InVT = InOp.getValueType();
|
||||
MVT::ValueType NewInVT = TLI.getTypeToTransformTo(InVT);
|
||||
|
||||
switch (getTypeAction(InVT)) {
|
||||
default:
|
||||
assert(false && "Unknown type action!");
|
||||
case Legal:
|
||||
break;
|
||||
case Promote:
|
||||
break;
|
||||
case Scalarize:
|
||||
// While it is tempting to extract the scalarized operand, check whether it
|
||||
// needs expansion, and if so process it in the Expand case below, there is
|
||||
// no guarantee that the scalarized operand has been processed yet. If it
|
||||
// hasn't then the call to GetExpandedOp will abort. So just give up.
|
||||
break;
|
||||
case Expand:
|
||||
// A scalar to vector conversion, where the scalar needs expansion.
|
||||
// Check that the vector is being split in two.
|
||||
if (MVT::getSizeInBits(NewInVT) == MVT::getSizeInBits(LoVT)) {
|
||||
// Convert each expanded piece of the scalar now.
|
||||
GetExpandedOp(InOp, Lo, Hi);
|
||||
if (TLI.isBigEndian())
|
||||
std::swap(Lo, Hi);
|
||||
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
||||
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case Split:
|
||||
// If the input is a vector that needs to be split, convert each split
|
||||
// piece of the input now.
|
||||
GetSplitOp(InOp, Lo, Hi);
|
||||
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
||||
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
// Lower the bit-convert to a store/load from the stack, then split the load.
|
||||
SDOperand Op = CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
|
||||
SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
|
||||
SplitRes_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
|
||||
}
|
||||
|
||||
@ -340,8 +367,11 @@ bool DAGTypeLegalizer::SplitOperand(SDNode *N, unsigned OpNo) {
|
||||
case ISD::STORE: Res = SplitOp_STORE(cast<StoreSDNode>(N), OpNo); break;
|
||||
case ISD::RET: Res = SplitOp_RET(N, OpNo); break;
|
||||
|
||||
case ISD::EXTRACT_SUBVECTOR: Res = SplitOp_EXTRACT_SUBVECTOR(N); break;
|
||||
case ISD::VECTOR_SHUFFLE: Res = SplitOp_VECTOR_SHUFFLE(N, OpNo); break;
|
||||
case ISD::BIT_CONVERT: Res = SplitOp_BIT_CONVERT(N); break;
|
||||
|
||||
case ISD::EXTRACT_VECTOR_ELT: Res = SplitOp_EXTRACT_VECTOR_ELT(N); break;
|
||||
case ISD::EXTRACT_SUBVECTOR: Res = SplitOp_EXTRACT_SUBVECTOR(N); break;
|
||||
case ISD::VECTOR_SHUFFLE: Res = SplitOp_VECTOR_SHUFFLE(N, OpNo); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -402,6 +432,72 @@ SDOperand DAGTypeLegalizer::SplitOp_RET(SDNode *N, unsigned OpNo) {
|
||||
return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Sign, Hi, Sign);
|
||||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::SplitOp_BIT_CONVERT(SDNode *N) {
|
||||
// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
|
||||
// end up being split all the way down to individual components. Convert the
|
||||
// split pieces into integers and reassemble.
|
||||
SDOperand Lo, Hi;
|
||||
GetSplitOp(N->getOperand(0), Lo, Hi);
|
||||
|
||||
unsigned LoBits = MVT::getSizeInBits(Lo.getValueType());
|
||||
Lo = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(LoBits), Lo);
|
||||
|
||||
unsigned HiBits = MVT::getSizeInBits(Hi.getValueType());
|
||||
Hi = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(HiBits), Hi);
|
||||
|
||||
if (TLI.isBigEndian())
|
||||
std::swap(Lo, Hi);
|
||||
|
||||
assert(LoBits == HiBits && "Do not know how to assemble odd sized vectors!");
|
||||
|
||||
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
|
||||
DAG.getNode(ISD::BUILD_PAIR,
|
||||
MVT::getIntegerType(LoBits+HiBits), Lo, Hi));
|
||||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
|
||||
SDOperand Vec = N->getOperand(0);
|
||||
SDOperand Idx = N->getOperand(1);
|
||||
MVT::ValueType VecVT = Vec.getValueType();
|
||||
|
||||
if (isa<ConstantSDNode>(Idx)) {
|
||||
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
|
||||
assert(IdxVal < MVT::getVectorNumElements(VecVT) &&
|
||||
"Invalid vector index!");
|
||||
|
||||
SDOperand Lo, Hi;
|
||||
GetSplitOp(Vec, Lo, Hi);
|
||||
|
||||
uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
|
||||
|
||||
if (IdxVal < LoElts)
|
||||
return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
|
||||
else
|
||||
return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi,
|
||||
DAG.getConstant(IdxVal - LoElts,
|
||||
Idx.getValueType()));
|
||||
}
|
||||
|
||||
// Store the vector to the stack and load back the required element.
|
||||
SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
|
||||
SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
|
||||
|
||||
// Add the offset to the index.
|
||||
MVT::ValueType EltVT = MVT::getVectorElementType(VecVT);
|
||||
unsigned EltSize = MVT::getSizeInBits(EltVT)/8; // FIXME: should be ABI size.
|
||||
Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
|
||||
DAG.getConstant(EltSize, Idx.getValueType()));
|
||||
|
||||
if (MVT::getSizeInBits(Idx.getValueType()) >
|
||||
MVT::getSizeInBits(TLI.getPointerTy()))
|
||||
Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
|
||||
else
|
||||
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
|
||||
|
||||
StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
|
||||
return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
|
||||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) {
|
||||
// We know that the extracted result type is legal. For now, assume the index
|
||||
// is a constant.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user