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Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-07 01:54:08 +00:00
parent 403d312c0f
commit 07a6d9391c
1 changed files with 15 additions and 9 deletions
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24
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -782,11 +782,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
AddDefaultPred(MIB.addMemOperand(MMO));
} else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
.addMemOperand(MMO));
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
.addFrameIndex(FI)
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
}
} else {
assert((RC == ARM::QQPRRegisterClass ||
@ -838,10 +841,13 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
} else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
.addFrameIndex(FI)
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
.addMemOperand(MMO));
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
.addFrameIndex(FI)
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
.addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
}
} else {
assert((RC == ARM::QQPRRegisterClass ||