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Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-03-07 00:18:12 +00:00
parent e75537a243
commit 084e179f09
3 changed files with 2 additions and 7 deletions
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5
include/llvm/CodeGen/ScheduleDAG.h
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@ -549,11 +549,6 @@ namespace llvm {
///
void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
/// BuildSchedGraph - Build SUnits and set up their Preds and Succs
/// to form the scheduling dependency graph.
///
virtual void BuildSchedGraph(AliasAnalysis *AA) = 0;
/// ComputeLatency - Compute node latency.
///
virtual void ComputeLatency(SUnit *SU) = 0;

2
lib/CodeGen/ScheduleDAGInstrs.h
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@ -245,7 +245,7 @@ namespace llvm {
/// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
/// input.
virtual void BuildSchedGraph(AliasAnalysis *AA);
void BuildSchedGraph(AliasAnalysis *AA);
/// AddSchedBarrierDeps - Add dependencies from instructions in the current
/// list of instructions being scheduled to scheduling barrier. We want to

2
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
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@ -79,7 +79,7 @@ namespace llvm {
/// are input. This SUnit graph is similar to the SelectionDAG, but
/// excludes nodes that aren't interesting to scheduling, and represents
/// flagged together nodes with a single SUnit.
virtual void BuildSchedGraph(AliasAnalysis *AA);
void BuildSchedGraph(AliasAnalysis *AA);
/// InitVRegCycleFlag - Set isVRegCycle if this node's single use is
/// CopyToReg and its only active data operands are CopyFromReg within a