RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-12 15:30:56 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Move MRI liveouts to XCore return instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2013-02-05 18:21:46 +00:00
parent 067e5a2a1a
commit 0873bc8419
2 changed files with 14 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -1249,15 +1249,11 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
// Analyze return values. // Analyze return values.
CCInfo.AnalyzeReturn(Outs, RetCC_XCore); CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
// If this is the first return lowered for this function, add
// the regs to the liveout set for the function.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
for (unsigned i = 0; i != RVLocs.size(); ++i)
if (RVLocs[i].isRegLoc())
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
SDValue Flag; SDValue Flag;
SmallVector<SDValue, 4> RetOps(1, Chain);
// Return on XCore is always a "retsp 0"
RetOps.push_back(DAG.getConstant(0, MVT::i32));
// Copy the result values into the output registers. // Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) { for (unsigned i = 0; i != RVLocs.size(); ++i) {
@ -1270,15 +1266,17 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
// guarantee that all emitted copies are // guarantee that all emitted copies are
// stuck together, avoiding something bad // stuck together, avoiding something bad
Flag = Chain.getValue(1); Flag = Chain.getValue(1);
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
} }
// Return on XCore is always a "retsp 0" RetOps[0] = Chain; // Update chain.
// Add the flag if we have it.
if (Flag.getNode()) if (Flag.getNode())
return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps.push_back(Flag);
Chain, DAG.getConstant(0, MVT::i32), Flag);
else // Return Void return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, &RetOps[0], RetOps.size());
Chain, DAG.getConstant(0, MVT::i32));
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

4
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -32,8 +32,8 @@ def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
SDNPVariadic]>; SDNPVariadic]>;
def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
[SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>; [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;
def SDT_XCoreBR_JT : SDTypeProfile<0, 2, def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;