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Move MRI liveouts to XCore return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1249,15 +1249,11 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
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// Analyze return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
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// If this is the first return lowered for this function, add
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// the regs to the liveout set for the function.
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if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
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for (unsigned i = 0; i != RVLocs.size(); ++i)
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if (RVLocs[i].isRegLoc())
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DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
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}
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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// Return on XCore is always a "retsp 0"
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RetOps.push_back(DAG.getConstant(0, MVT::i32));
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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@ -1270,15 +1266,17 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
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// guarantee that all emitted copies are
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// stuck together, avoiding something bad
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Flag = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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}
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// Return on XCore is always a "retsp 0"
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RetOps[0] = Chain; // Update chain.
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// Add the flag if we have it.
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if (Flag.getNode())
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RetOps.push_back(Flag);
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return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
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Chain, DAG.getConstant(0, MVT::i32), Flag);
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else // Return Void
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return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
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Chain, DAG.getConstant(0, MVT::i32));
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&RetOps[0], RetOps.size());
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}
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//===----------------------------------------------------------------------===//
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@ -33,7 +33,7 @@ def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
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SDNPVariadic]>;
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def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
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[SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>;
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[SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;
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def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
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[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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