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AArch64: strengthen Darwin ABI alignment assumptions
A global variable without an explicit alignment specified should be assumed to be ABI-aligned according to its type, like on other platforms. This allows us to use better memory operations when accessing it. rdar://18533701 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223180 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -615,7 +615,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
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unsigned Alignment = GV->getAlignment();
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const DataLayout *DL = TLI->getDataLayout();
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Type *Ty = GV->getType()->getElementType();
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if (Alignment == 0 && Ty->isSized() && !Subtarget->isTargetDarwin())
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if (Alignment == 0 && Ty->isSized())
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Alignment = DL->getABITypeAlignment(Ty);
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if (Alignment >= Size)
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@ -41,8 +41,7 @@ entry:
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; PROMOTED-LABEL: test2:
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; In stress mode, constant vector are promoted
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; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst[0-9]+]]@PAGE
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; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
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; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
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; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
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; Destination register is defined by ABI
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; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
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; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
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@ -72,15 +71,13 @@ define <16 x i8> @test3(<16 x i8> %arg, i32 %path) {
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; Since, the constant is the same as the previous function,
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; the same address must be used
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; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
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; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
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; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
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; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
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; Destination register is defined by ABI
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; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
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; PROMOTED-NEXT: cbnz w0, [[LABEL:LBB.*]]
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; Next BB
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; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV2:__PromotedConst[0-9]+]]@PAGE
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; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV2]]@PAGEOFF
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; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[BASEADDR]]]
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; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTV2]]@PAGEOFF]
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; Next BB
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; PROMOTED-NEXT: [[LABEL]]:
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; PROMOTED-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
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@ -136,8 +133,7 @@ define <16 x i8> @test4(<16 x i8> %arg, i32 %path) {
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; Since, the constant is the same as the previous function,
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; the same address must be used
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; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
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; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
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; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
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; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
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; Destination register is defined by ABI
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; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
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; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
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@ -185,8 +181,7 @@ define <16 x i8> @test5(<16 x i8> %arg, i32 %path) {
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; Since, the constant is the same as the previous function,
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; the same address must be used
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; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
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; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
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; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
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; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
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; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
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; Next BB
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; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
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@ -11,6 +11,7 @@
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@n = internal global i32 0, align 4
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define void @f1(i32 %a1, i32 %a2) {
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;CHECK-APPLE-IOS-NOT: adrp
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;CHECK-APPLE-IOS: adrp x8, __MergedGlobals@PAGE
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;CHECK-APPLE-IOS-NOT: adrp
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;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals@PAGEOFF
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@ -8,6 +8,7 @@
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define void @f1(i32 %a1, i32 %a2) {
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;CHECK-APPLE-IOS-LABEL: _f1:
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;CHECK-APPLE-IOS-NOT: adrp
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;CHECK-APPLE-IOS: adrp x8, __MergedGlobals_x@PAGE
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;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals_x@PAGEOFF
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;CHECK-APPLE-IOS-NOT: adrp
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