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Completely eliminate def&use operands. Now a register operand is EITHER a

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def operand or a use operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-09-05 02:31:13 +00:00
parent 2926869b4a
commit 09e460662a
10 changed files with 78 additions and 106 deletions
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56
include/llvm/CodeGen/MachineInstr.h
View File

@ -38,26 +38,6 @@ template <typename T> struct ilist;
// Representation of each machine instruction operand. // Representation of each machine instruction operand.
// //
struct MachineOperand { struct MachineOperand {
private:
// Bit fields of the flags variable used for different operand properties
enum {
DEFFLAG = 0x01, // this is a def of the operand
USEFLAG = 0x02 // this is a use of the operand
};
public:
// UseType - This enum describes how the machine operand is used by
// the instruction. Note that the MachineInstr/Operator class
// currently uses bool arguments to represent this information
// instead of an enum. Eventually this should change over to use
// this _easier to read_ representation instead.
//
enum UseType {
Use = USEFLAG, /// only read
Def = DEFFLAG, /// only written
UseAndDef = Use | Def /// read AND written
};
enum MachineOperandType { enum MachineOperandType {
MO_Register, // Register operand. MO_Register, // Register operand.
MO_Immediate, // Immediate Operand MO_Immediate, // Immediate Operand
@ -78,8 +58,8 @@ private:
int64_t immedVal; // For MO_Immediate and MO_*Index. int64_t immedVal; // For MO_Immediate and MO_*Index.
} contents; } contents;
char flags; // see bit field definitions above MachineOperandType opType:8; // Discriminate the union.
MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. bool IsDef : 1; // True if this is a def, false if this is a use.
/// offset - Offset to address of global or external, only valid for /// offset - Offset to address of global or external, only valid for
/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
@ -95,7 +75,7 @@ public:
const MachineOperand &operator=(const MachineOperand &MO) { const MachineOperand &operator=(const MachineOperand &MO) {
contents = MO.contents; contents = MO.contents;
flags = MO.flags; IsDef = MO.IsDef;
opType = MO.opType; opType = MO.opType;
offset = MO.offset; offset = MO.offset;
return *this; return *this;
@ -105,10 +85,6 @@ public:
/// ///
MachineOperandType getType() const { return opType; } MachineOperandType getType() const { return opType; }
/// getUseType - Returns the MachineOperandUseType of this operand.
///
UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); }
/// Accessors that tell you what kind of MachineOperand you're looking at. /// Accessors that tell you what kind of MachineOperand you're looking at.
/// ///
bool isReg() const { return opType == MO_Register; } bool isReg() const { return opType == MO_Register; }
@ -167,13 +143,10 @@ public:
return contents.SymbolName; return contents.SymbolName;
} }
/// MachineOperand methods for testing that work on any kind of bool isUse() const { return !IsDef; }
/// MachineOperand... bool isDef() const { return IsDef; }
/// void setIsUse() { IsDef = false; }
bool isUse() const { return flags & USEFLAG; } void setIsDef() { IsDef = true; }
bool isDef() const { return flags & DEFFLAG; }
MachineOperand &setUse() { flags |= USEFLAG; return *this; }
MachineOperand &setDef() { flags |= DEFFLAG; return *this; }
/// getReg - Returns the register number. /// getReg - Returns the register number.
/// ///
@ -216,9 +189,10 @@ public:
/// ChangeToRegister - Replace this operand with a new register operand of /// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already, /// the specified value. If an operand is known to be an register already,
/// the setReg method should be used. /// the setReg method should be used.
void ChangeToRegister(unsigned Reg) { void ChangeToRegister(unsigned Reg, bool isDef) {
opType = MO_Register; opType = MO_Register;
contents.RegNo = Reg; contents.RegNo = Reg;
IsDef = isDef;
} }
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
@ -307,11 +281,10 @@ public:
/// addRegOperand - Add a register operand. /// addRegOperand - Add a register operand.
/// ///
void addRegOperand(unsigned Reg, void addRegOperand(unsigned Reg, bool IsDef) {
MachineOperand::UseType UTy = MachineOperand::Use) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_Register; Op.opType = MachineOperand::MO_Register;
Op.flags = UTy; Op.IsDef = IsDef;
Op.contents.RegNo = Reg; Op.contents.RegNo = Reg;
Op.offset = 0; Op.offset = 0;
} }
@ -322,7 +295,6 @@ public:
void addImmOperand(int64_t Val) { void addImmOperand(int64_t Val) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_Immediate; Op.opType = MachineOperand::MO_Immediate;
Op.flags = 0;
Op.contents.immedVal = Val; Op.contents.immedVal = Val;
Op.offset = 0; Op.offset = 0;
} }
@ -330,7 +302,6 @@ public:
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_MachineBasicBlock; Op.opType = MachineOperand::MO_MachineBasicBlock;
Op.flags = 0;
Op.contents.MBB = MBB; Op.contents.MBB = MBB;
Op.offset = 0; Op.offset = 0;
} }
@ -340,7 +311,6 @@ public:
void addFrameIndexOperand(unsigned Idx) { void addFrameIndexOperand(unsigned Idx) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_FrameIndex; Op.opType = MachineOperand::MO_FrameIndex;
Op.flags = 0;
Op.contents.immedVal = Idx; Op.contents.immedVal = Idx;
Op.offset = 0; Op.offset = 0;
} }
@ -351,7 +321,6 @@ public:
void addConstantPoolIndexOperand(unsigned Idx, int Offset) { void addConstantPoolIndexOperand(unsigned Idx, int Offset) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_ConstantPoolIndex; Op.opType = MachineOperand::MO_ConstantPoolIndex;
Op.flags = 0;
Op.contents.immedVal = Idx; Op.contents.immedVal = Idx;
Op.offset = Offset; Op.offset = Offset;
} }
@ -362,7 +331,6 @@ public:
void addJumpTableIndexOperand(unsigned Idx) { void addJumpTableIndexOperand(unsigned Idx) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_JumpTableIndex; Op.opType = MachineOperand::MO_JumpTableIndex;
Op.flags = 0;
Op.contents.immedVal = Idx; Op.contents.immedVal = Idx;
Op.offset = 0; Op.offset = 0;
} }
@ -370,7 +338,6 @@ public:
void addGlobalAddressOperand(GlobalValue *GV, int Offset) { void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_GlobalAddress; Op.opType = MachineOperand::MO_GlobalAddress;
Op.flags = 0;
Op.contents.GV = GV; Op.contents.GV = GV;
Op.offset = Offset; Op.offset = Offset;
} }
@ -380,7 +347,6 @@ public:
void addExternalSymbolOperand(const char *SymName) { void addExternalSymbolOperand(const char *SymName) {
MachineOperand &Op = AddNewOperand(); MachineOperand &Op = AddNewOperand();
Op.opType = MachineOperand::MO_ExternalSymbol; Op.opType = MachineOperand::MO_ExternalSymbol;
Op.flags = 0;
Op.contents.SymbolName = SymName; Op.contents.SymbolName = SymName;
Op.offset = 0; Op.offset = 0;
} }

16
include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -33,10 +33,8 @@ public:
/// addReg - Add a new virtual register operand... /// addReg - Add a new virtual register operand...
/// ///
const MachineInstrBuilder &addReg( const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const {
int RegNo, MI->addRegOperand(RegNo, isDef);
MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addRegOperand(RegNo, Ty);
return *this; return *this;
} }
@ -92,12 +90,10 @@ inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands) {
/// destination virtual register. NumOperands is the number of additional add* /// destination virtual register. NumOperands is the number of additional add*
/// calls that are expected, not including the destination register. /// calls that are expected, not including the destination register.
/// ///
inline MachineInstrBuilder BuildMI( inline MachineInstrBuilder
int Opcode, unsigned NumOperands, BuildMI(int Opcode, unsigned NumOperands, unsigned DestReg) {
unsigned DestReg,
MachineOperand::UseType useType = MachineOperand::Def) {
return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1)) return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1))
.addReg(DestReg, useType); .addReg(DestReg, true);
} }
/// BuildMI - This version of the builder inserts the newly-built /// BuildMI - This version of the builder inserts the newly-built
@ -112,7 +108,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
unsigned DestReg) { unsigned DestReg) {
MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1); MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1);
BB.insert(I, MI); BB.insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def); return MachineInstrBuilder(MI).addReg(DestReg, true);
} }
/// BuildMI - This version of the builder inserts the newly-built /// BuildMI - This version of the builder inserts the newly-built

16
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -255,11 +255,11 @@ static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
// the machine instruction. // the machine instruction.
unsigned ResultReg = unsigned ResultReg =
RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0)); RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
MI->addRegOperand(ResultReg, MachineOperand::Def); MI->addRegOperand(ResultReg, true);
for (unsigned i = 1; i != NumResults; ++i) { for (unsigned i = 1; i != NumResults; ++i) {
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i); const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!"); assert(RC && "Isn't a register operand!");
MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def); MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
} }
return ResultReg; return ResultReg;
} }
@ -291,7 +291,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
// Get/emit the operand. // Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap); unsigned VReg = getVR(Op, VRBaseMap);
MI->addRegOperand(VReg, MachineOperand::Use); MI->addRegOperand(VReg, false);
// Verify that it is right. // Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@ -307,7 +307,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
MI->addImmOperand(C->getValue()); MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R = } else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) { dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), MachineOperand::Use); MI->addRegOperand(R->getReg(), false);
} else if (GlobalAddressSDNode *TGA = } else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) { dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
@ -349,7 +349,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
Op.getValueType() != MVT::Flag && Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!"); "Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap); unsigned VReg = getVR(Op, VRBaseMap);
MI->addRegOperand(VReg, MachineOperand::Use); MI->addRegOperand(VReg, false);
// Verify that it is right. // Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@ -402,7 +402,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) { if (MRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg; VRBase = Reg;
MI->addRegOperand(Reg, MachineOperand::Def); MI->addRegOperand(Reg, true);
break; break;
} }
} }
@ -529,13 +529,13 @@ void ScheduleDAG::EmitNode(SDNode *Node,
case 1: // Use of register. case 1: // Use of register.
for (; NumVals; --NumVals, ++i) { for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addRegOperand(Reg, MachineOperand::Use); MI->addRegOperand(Reg, false);
} }
break; break;
case 2: // Def of register. case 2: // Def of register.
for (; NumVals; --NumVals, ++i) { for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addRegOperand(Reg, MachineOperand::Def); MI->addRegOperand(Reg, true);
} }
break; break;
case 3: { // Immediate. case 3: { // Immediate.

8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -3547,7 +3547,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
MachineInstr *PHI = PHINodesToUpdate[i].first; MachineInstr *PHI = PHINodesToUpdate[i].first;
assert(PHI->getOpcode() == TargetInstrInfo::PHI && assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!"); "This is not a machine PHI node that we are updating!");
PHI->addRegOperand(PHINodesToUpdate[i].second); PHI->addRegOperand(PHINodesToUpdate[i].second, false);
PHI->addMachineBasicBlockOperand(BB); PHI->addMachineBasicBlockOperand(BB);
} }
return; return;
@ -3576,11 +3576,11 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
assert(PHI->getOpcode() == TargetInstrInfo::PHI && assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!"); "This is not a machine PHI node that we are updating!");
if (PHIBB == JT.Default) { if (PHIBB == JT.Default) {
PHI->addRegOperand(PHINodesToUpdate[pi].second); PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(RangeBB); PHI->addMachineBasicBlockOperand(RangeBB);
} }
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
PHI->addRegOperand(PHINodesToUpdate[pi].second); PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BB); PHI->addMachineBasicBlockOperand(BB);
} }
} }
@ -3610,7 +3610,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
assert(PHI->getOpcode() == TargetInstrInfo::PHI && assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!"); "This is not a machine PHI node that we are updating!");
if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) { if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
PHI->addRegOperand(PHINodesToUpdate[pi].second); PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BB); PHI->addMachineBasicBlockOperand(BB);
} }
} }

4
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -107,7 +107,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
assert (Offset >= 0); assert (Offset >= 0);
if (Offset < 4096) { if (Offset < 4096) {
// Replace the FrameIndex with r13 // Replace the FrameIndex with r13
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13); MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false);
// Replace the ldr offset with Offset // Replace the ldr offset with Offset
MI.getOperand(OffIdx).ChangeToImmediate(Offset); MI.getOperand(OffIdx).ChangeToImmediate(Offset);
} else { } else {
@ -117,7 +117,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset); BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
// Replace the FrameIndex with r12 // Replace the FrameIndex with r12
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12); MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
} }
} }

44
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -67,14 +67,18 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx, unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
//<< FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
if (RC == Alpha::F4RCRegisterClass) if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::STS, 3)
.addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass) else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::STT, 3)
.addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass) else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::STQ, 3)
.addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else else
abort(); abort();
} }
@ -84,13 +88,17 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx, unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
//<< FrameIdx << "\n";
if (RC == Alpha::F4RCRegisterClass) if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass) else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass) else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else else
abort(); abort();
} }
@ -243,7 +251,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
int FrameIndex = MI.getOperand(i).getFrameIndex(); int FrameIndex = MI.getOperand(i).getFrameIndex();
// Add the base register of R30 (SP) or R15 (FP). // Add the base register of R30 (SP) or R15 (FP).
MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30); MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
// Now add the frame object offset to the offset from the virtual frame index. // Now add the frame object offset to the offset from the virtual frame index.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@ -256,11 +264,12 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
" for stack size: " << MF.getFrameInfo()->getStackSize() << "\n"); " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
if (Offset > IMM_HIGH || Offset < IMM_LOW) { if (Offset > IMM_HIGH || Offset < IMM_LOW) {
DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n"); DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
//so in this case, we need to use a temporary register, and move the original << Offset << "\n");
//inst off the SP/FP //so in this case, we need to use a temporary register, and move the
//original inst off the SP/FP
//fix up the old: //fix up the old:
MI.getOperand(i + 1).ChangeToRegister(Alpha::R28); MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
//insert the new //insert the new
MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
@ -335,9 +344,11 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
//now if we need to, save the old FP and set the new //now if we need to, save the old FP and set the new
if (FP) if (FP)
{ {
BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); BuildMI(MBB, MBBI, Alpha::STQ, 3)
.addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
//this must be the last instr in the prolog //this must be the last instr in the prolog
BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30); BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15)
.addReg(Alpha::R30).addReg(Alpha::R30);
} }
} }
@ -346,7 +357,8 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo(); const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end()); MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp assert(MBBI->getOpcode() == Alpha::RETDAG ||
MBBI->getOpcode() == Alpha::RETDAGp
&& "Can only insert epilog into returning blocks"); && "Can only insert epilog into returning blocks");
bool FP = hasFP(MF); bool FP = hasFP(MF);

18
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -85,7 +85,8 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
// (SrcReg) DestReg = cmp.eq.unc(r0, r0) // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg)
.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
else // otherwise, MOV works (for both gen. regs and FP regs) else // otherwise, MOV works (for both gen. regs and FP regs)
BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg); BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
} }
@ -170,7 +171,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
// choose a base register: ( hasFP? framepointer : stack pointer ) // choose a base register: ( hasFP? framepointer : stack pointer )
unsigned BaseRegister = FP ? IA64::r5 : IA64::r12; unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
// Add the base register // Add the base register
MI.getOperand(i).ChangeToRegister(BaseRegister); MI.getOperand(i).ChangeToRegister(BaseRegister, false);
// Now add the frame object offset to the offset from r1. // Now add the frame object offset to the offset from r1.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@ -182,19 +183,15 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
// XXX: we use 'r22' as another hack+slash temporary register here :( // XXX: we use 'r22' as another hack+slash temporary register here :(
if (Offset <= 8191 && Offset >= -8192) { // smallish offset if (Offset <= 8191 && Offset >= -8192) { // smallish offset
//fix up the old: // Fix up the old:
MI.getOperand(i).ChangeToRegister(IA64::r22); MI.getOperand(i).ChangeToRegister(IA64::r22, false);
MI.getOperand(i).setUse(); // mark r22 as being used
// (the bundler wants to know this)
//insert the new //insert the new
MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22) MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
.addReg(BaseRegister).addImm(Offset); .addReg(BaseRegister).addImm(Offset);
MBB.insert(II, nMI); MBB.insert(II, nMI);
} else { // it's big } else { // it's big
//fix up the old: //fix up the old:
MI.getOperand(i).ChangeToRegister(IA64::r22); MI.getOperand(i).ChangeToRegister(IA64::r22, false);
MI.getOperand(i).setUse(); // mark r22 as being used
// (the bundler wants to know this)
MachineInstr* nMI; MachineInstr* nMI;
nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset); nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
MBB.insert(II, nMI); MBB.insert(II, nMI);
@ -242,7 +239,8 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed; unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
// XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB) // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
// a pseudo_alloc in the MBB)
unsigned dstRegOfPseudoAlloc; unsigned dstRegOfPseudoAlloc;
for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) { for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
assert(MBBI != MBB.end()); assert(MBBI != MBB.end());

6
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -421,7 +421,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
int FrameIndex = MI.getOperand(i).getFrameIndex(); int FrameIndex = MI.getOperand(i).getFrameIndex();
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1); MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
// Take into account whether it's an add or mem instruction // Take into account whether it's an add or mem instruction
unsigned OffIdx = (i == 2) ? 1 : 2; unsigned OffIdx = (i == 2) ? 1 : 2;
@ -466,8 +466,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
"No indexed form of load or store available!"); "No indexed form of load or store available!");
unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
MI.setOpcode(NewOpcode); MI.setOpcode(NewOpcode);
MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg()); MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
MI.getOperand(2).ChangeToRegister(PPC::R0); MI.getOperand(2).ChangeToRegister(PPC::R0, false);
} else { } else {
if (isIXAddr) { if (isIXAddr) {
assert((Offset & 3) == 0 && "Invalid frame offset!"); assert((Offset & 3) == 0 && "Invalid frame offset!");

4
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -147,7 +147,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
if (Offset >= -4096 && Offset <= 4095) { if (Offset >= -4096 && Offset <= 4095) {
// If the offset is small enough to fit in the immediate field, directly // If the offset is small enough to fit in the immediate field, directly
// encode it. // encode it.
MI.getOperand(i).ChangeToRegister(SP::I6); MI.getOperand(i).ChangeToRegister(SP::I6, false);
MI.getOperand(i+1).ChangeToImmediate(Offset); MI.getOperand(i+1).ChangeToImmediate(Offset);
} else { } else {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
@ -158,7 +158,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
BuildMI(*MI.getParent(), II, SP::ADDrr, 2, BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
SP::G1).addReg(SP::G1).addReg(SP::I6); SP::G1).addReg(SP::G1).addReg(SP::I6);
// Insert: G1+%lo(offset) into the user. // Insert: G1+%lo(offset) into the user.
MI.getOperand(i).ChangeToRegister(SP::G1); MI.getOperand(i).ChangeToRegister(SP::G1, false);
MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
} }
} }

4
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -168,7 +168,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
assert(MO.isReg() && "Expected to fold into reg operand!"); assert(MO.isReg() && "Expected to fold into reg operand!");
MIB = addFrameReference(MIB, FrameIndex); MIB = addFrameReference(MIB, FrameIndex);
} else if (MO.isReg()) } else if (MO.isReg())
MIB = MIB.addReg(MO.getReg(), MO.getUseType()); MIB = MIB.addReg(MO.getReg(), MO.isDef());
else if (MO.isImm()) else if (MO.isImm())
MIB = MIB.addImm(MO.getImm()); MIB = MIB.addImm(MO.getImm());
else if (MO.isGlobalAddress()) else if (MO.isGlobalAddress())
@ -795,7 +795,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
// This must be part of a four operand memory reference. Replace the // This must be part of a four operand memory reference. Replace the
// FrameIndex with base register with EBP. Add add an offset to the offset. // FrameIndex with base register with EBP. Add add an offset to the offset.
MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP); MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP, false);
// Now add the frame object offset to the offset from EBP. // Now add the frame object offset to the offset from EBP.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +