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SelectionDAGBuilder: style fixes (add space between end parentheses and open brace)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185768 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1476,7 +1476,7 @@ void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
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/// If we should emit this as a bunch of and/or'd together conditions, return
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/// false.
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bool
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SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
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SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
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if (Cases.size() != 2) return true;
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// If this is two comparisons of the same values or'd or and'd together, they
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@ -2039,12 +2039,11 @@ bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
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// The last case block won't fall through into 'NextBlock' if we emit the
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// branches in this order. See if rearranging a case value would help.
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// We start at the bottom as it's the case with the least weight.
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for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
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for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
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if (I->BB == NextBlock) {
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std::swap(*I, BackCase);
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break;
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}
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}
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}
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// Create a CaseBlock record representing a conditional branch to
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@ -2227,8 +2226,8 @@ bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
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bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock *Default,
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MachineBasicBlock *SwitchBB) {
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MachineBasicBlock* Default,
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MachineBasicBlock* SwitchBB) {
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// Get the MachineFunction which holds the current MBB. This is used when
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// inserting any additional MBBs necessary to represent the switch.
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MachineFunction *CurMF = FuncInfo.MF;
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@ -2363,7 +2362,7 @@ bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default,
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MachineBasicBlock *SwitchBB){
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MachineBasicBlock* SwitchBB) {
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const TargetLowering *TLI = TM.getTargetLowering();
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EVT PTy = TLI->getPointerTy();
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unsigned IntPtrBits = PTy.getSizeInBits();
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@ -2793,7 +2792,7 @@ void SelectionDAGBuilder::visitFPTrunc(const User &I) {
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DAG.getTargetConstant(0, TLI->getPointerTy())));
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}
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void SelectionDAGBuilder::visitFPExt(const User &I){
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void SelectionDAGBuilder::visitFPExt(const User &I) {
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// FPExt is never a no-op cast, no need to check
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SDValue N = getValue(I.getOperand(0));
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EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
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@ -2821,7 +2820,7 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) {
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setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
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}
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void SelectionDAGBuilder::visitSIToFP(const User &I){
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void SelectionDAGBuilder::visitSIToFP(const User &I) {
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// SIToFP is never a no-op cast, no need to check
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SDValue N = getValue(I.getOperand(0));
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EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
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@ -4354,7 +4353,8 @@ static unsigned getTruncatedArgReg(const SDValue &N) {
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return 0;
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const SDValue &Ext = N.getOperand(0);
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if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
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if (Ext.getOpcode() == ISD::AssertZext ||
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Ext.getOpcode() == ISD::AssertSext) {
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const SDValue &CFR = Ext.getOperand(0);
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if (CFR.getOpcode() == ISD::CopyFromReg)
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return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
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@ -4922,7 +4922,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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case Intrinsic::fmuladd: {
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EVT VT = TLI->getValueType(I.getType());
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if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
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TLI->isFMAFasterThanMulAndAdd(VT)){
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TLI->isFMAFasterThanMulAndAdd(VT)) {
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setValue(&I, DAG.getNode(ISD::FMA, sdl,
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getValue(I.getArgOperand(0)).getValueType(),
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getValue(I.getArgOperand(0)),
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