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Fix 64-bit atomic operations in Thumb mode.
The ARM and Thumb variants of LDREXD and STREXD have different constraints and take different operands. Previously the code expanding atomic operations didn't take this into account and asserted in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
e6482fabd2
commit
0adfdedacb
@ -5969,9 +5969,6 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
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}
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unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
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unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *contBB = 0, *cont2BB = 0;
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if (IsCmpxchg || IsMinMax)
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@ -6009,42 +6006,26 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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// cmp storesuccess, #0
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// bne- loopMBB
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// fallthrough --> exitMBB
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//
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// Note that the registers are explicitly specified because there is not any
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// way to force the register allocator to allocate a register pair.
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//
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// FIXME: The hardcoded registers are not necessary for Thumb2, but we
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// need to properly enforce the restriction that the two output registers
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// for ldrexd must be different.
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BB = loopMBB;
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// Load
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unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned GPRPair1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned GPRPair2;
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if (IsMinMax) {
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//We need an extra double register for doing min/max.
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unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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GPRPair2 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), undef);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(undef)
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.addReg(vallo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair2)
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.addReg(r1)
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.addReg(valhi)
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.addImm(ARM::gsub_1);
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if (isThumb2) {
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2LDREXD))
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.addReg(destlo, RegState::Define)
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.addReg(desthi, RegState::Define)
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.addReg(ptr));
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} else {
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unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDREXD))
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.addReg(GPRPair0, RegState::Define).addReg(ptr));
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// Copy r2/r3 into dest. (This copy will normally be coalesced.)
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo)
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.addReg(GPRPair0, 0, ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi)
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.addReg(GPRPair0, 0, ARM::gsub_1);
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}
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
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.addReg(GPRPair0, RegState::Define).addReg(ptr));
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// Copy r2/r3 into dest. (This copy will normally be coalesced.)
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo)
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.addReg(GPRPair0, 0, ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi)
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.addReg(GPRPair0, 0, ARM::gsub_1);
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unsigned StoreLo, StoreHi;
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if (IsCmpxchg) {
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// Add early exit
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for (unsigned i = 0; i < 2; i++) {
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@ -6060,19 +6041,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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}
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// Copy to physregs for strexd
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unsigned setlo = MI->getOperand(5).getReg();
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unsigned sethi = MI->getOperand(6).getReg();
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unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), undef);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(undef)
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.addReg(setlo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
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.addReg(r1)
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.addReg(sethi)
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.addImm(ARM::gsub_1);
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StoreLo = MI->getOperand(5).getReg();
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StoreHi = MI->getOperand(6).getReg();
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} else if (Op1) {
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// Perform binary operation
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unsigned tmpRegLo = MRI.createVirtualRegister(TRC);
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@ -6084,32 +6054,13 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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.addReg(desthi).addReg(valhi))
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.addReg(IsMinMax ? ARM::CPSR : 0, getDefRegState(IsMinMax));
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unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(UndefPair)
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.addReg(tmpRegLo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
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.addReg(r1)
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.addReg(tmpRegHi)
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.addImm(ARM::gsub_1);
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StoreLo = tmpRegLo;
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StoreHi = tmpRegHi;
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} else {
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// Copy to physregs for strexd
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unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(UndefPair)
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.addReg(vallo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
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.addReg(r1)
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.addReg(valhi)
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.addImm(ARM::gsub_1);
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StoreLo = vallo;
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StoreHi = valhi;
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}
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unsigned GPRPairStore = GPRPair1;
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if (IsMinMax) {
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// Compare and branch to exit block.
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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@ -6117,12 +6068,33 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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BB->addSuccessor(exitMBB);
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BB->addSuccessor(contBB);
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BB = contBB;
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GPRPairStore = GPRPair2;
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StoreLo = vallo;
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StoreHi = valhi;
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}
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// Store
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
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.addReg(GPRPairStore).addReg(ptr));
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if (isThumb2) {
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2STREXD), storesuccess)
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.addReg(StoreLo).addReg(StoreHi).addReg(ptr));
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} else {
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// Marshal a pair...
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unsigned StorePair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(UndefPair)
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.addReg(StoreLo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), StorePair)
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.addReg(r1)
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.addReg(StoreHi)
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.addImm(ARM::gsub_1);
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// ...and store it
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::STREXD), storesuccess)
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.addReg(StorePair).addReg(ptr));
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}
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// Cmp+jump
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
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.addReg(storesuccess).addImm(0));
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB
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define i64 @test1(i64* %ptr, i64 %val) {
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; CHECK: test1:
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@ -10,6 +11,17 @@ define i64 @test1(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test1:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = atomicrmw add i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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@ -24,6 +36,17 @@ define i64 @test2(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test2:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = atomicrmw sub i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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@ -38,6 +61,17 @@ define i64 @test3(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test3:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: and.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = atomicrmw and i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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@ -52,6 +86,17 @@ define i64 @test4(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test4:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = atomicrmw or i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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@ -66,6 +111,17 @@ define i64 @test5(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test5:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = atomicrmw xor i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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@ -78,6 +134,15 @@ define i64 @test6(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test6:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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@ -93,6 +158,19 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test7:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: cmp [[REG1]]
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; CHECK-THUMB: it eq
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; CHECK-THUMB: cmpeq [[REG2]]
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; CHECK-THUMB: bne
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
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ret i64 %r
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}
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@ -109,6 +187,18 @@ define i64 @test8(i64* %ptr) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test8:
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: cmp [[REG1]]
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; CHECK-THUMB: it eq
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; CHECK-THUMB: cmpeq [[REG2]]
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; CHECK-THUMB: bne
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = load atomic i64* %ptr seq_cst, align 8
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ret i64 %r
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}
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@ -123,6 +213,15 @@ define void @test9(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test9:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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store atomic i64 %val, i64* %ptr seq_cst, align 8
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ret void
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}
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@ -138,6 +237,18 @@ define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test10:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
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; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
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; CHECK-THUMB: blt
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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%r = atomicrmw min i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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@ -153,6 +264,19 @@ define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK-THUMB: test11:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
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; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
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; CHECK-THUMB: blo
|
||||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK-THUMB: cmp
|
||||
; CHECK-THUMB: bne
|
||||
; CHECK-THUMB: dmb ish
|
||||
|
||||
%r = atomicrmw umin i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
@ -168,6 +292,18 @@ define i64 @test12(i64* %ptr, i64 %val) {
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK-THUMB: test12:
|
||||
; CHECK-THUMB: dmb ish
|
||||
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
|
||||
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
|
||||
; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
|
||||
; CHECK-THUMB: bge
|
||||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK-THUMB: cmp
|
||||
; CHECK-THUMB: bne
|
||||
; CHECK-THUMB: dmb ish
|
||||
|
||||
%r = atomicrmw max i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
@ -183,6 +319,17 @@ define i64 @test13(i64* %ptr, i64 %val) {
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK-THUMB: test13:
|
||||
; CHECK-THUMB: dmb ish
|
||||
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
|
||||
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
|
||||
; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
|
||||
; CHECK-THUMB: bhs
|
||||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK-THUMB: cmp
|
||||
; CHECK-THUMB: bne
|
||||
; CHECK-THUMB: dmb ish
|
||||
%r = atomicrmw umax i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user