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Fix CellSPU vector shuffles, again.

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Some cases of lowering to rotate were miscompiled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila 2010-09-08 11:53:38 +00:00
parent c8ae35a8e8
commit 0b4ab0cfe0
2 changed files with 33 additions and 7 deletions
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14
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -1735,9 +1735,9 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
unsigned CurrElt = 0; unsigned CurrElt = 0;
unsigned MaxElts = VecVT.getVectorNumElements(); unsigned MaxElts = VecVT.getVectorNumElements();
unsigned PrevElt = 0; unsigned PrevElt = 0;
unsigned V0Elt = 0;
bool monotonic = true; bool monotonic = true;
bool rotate = true; bool rotate = true;
int rotamt;
EVT maskVT; // which of the c?d instructions to use EVT maskVT; // which of the c?d instructions to use
if (EltVT == MVT::i8) { if (EltVT == MVT::i8) {
@ -1781,14 +1781,13 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
if (PrevElt > 0 && SrcElt < MaxElts) { if (PrevElt > 0 && SrcElt < MaxElts) {
if ((PrevElt == SrcElt - 1) if ((PrevElt == SrcElt - 1)
|| (PrevElt == MaxElts - 1 && SrcElt == 0)) { || (PrevElt == MaxElts - 1 && SrcElt == 0)) {
rotamt = SrcElt-i;
PrevElt = SrcElt; PrevElt = SrcElt;
if (SrcElt == 0)
V0Elt = i;
} else { } else {
rotate = false; rotate = false;
} }
} else if (i == 0) { } else if (i == 0 || (PrevElt==0 && SrcElt==1)) {
// First time through, need to keep track of previous element // First time or after a "wrap around"
PrevElt = SrcElt; PrevElt = SrcElt;
} else { } else {
// This isn't a rotation, takes elements from vector 2 // This isn't a rotation, takes elements from vector 2
@ -1813,8 +1812,9 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1, return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
ShufMaskOp); ShufMaskOp);
} else if (rotate) { } else if (rotate) {
int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8; if (rotamt < 0)
rotamt +=MaxElts;
rotamt *= EltVT.getSizeInBits()/8;
return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(), return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
V1, DAG.getConstant(rotamt, MVT::i16)); V1, DAG.getConstant(rotamt, MVT::i16));
} else { } else {

26
test/CodeGen/CellSPU/shuffles.ll
View File

@ -39,3 +39,29 @@ define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
ret <4 x float> %rv ret <4 x float> %rv
} }
define <2 x i32> @test_v2i32(<4 x i32>%vec)
{
;CHECK: rotqbyi $3, $3, 4
;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32><i32 1,i32 2>
ret <2 x i32> %rv
}
define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec)
{
;CHECK: rotqbyi $3, $3, 8
;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
<4 x i32> <i32 2,i32 3,i32 0, i32 1>
ret <4 x i32> %rv
}
define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec)
{
;CHECK: rotqbyi $3, $3, 4
;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
<4 x i32> <i32 1,i32 2,i32 3, i32 0>
ret <4 x i32> %rv
}