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Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate

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a case involving EOR, so I only added a test for ORR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129610 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-04-15 21:24:38 +00:00
parent 3e03e5d2a9
commit 0cb11ac32f
2 changed files with 31 additions and 4 deletions
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10
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -1642,7 +1642,15 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
case ARM::ANDrr:
case ARM::ANDri:
case ARM::t2ANDrr:
case ARM::t2ANDri: {
case ARM::t2ANDri:
case ARM::ORRrr:
case ARM::ORRri:
case ARM::t2ORRrr:
case ARM::t2ORRri:
case ARM::EORrr:
case ARM::EORri:
case ARM::t2EORrr:
case ARM::t2EORri: {
// Scan forward for the use of CPSR, if it's a conditional code requires
// checking of V bit, then this is not safe to do. If we can't find the
// CPSR use (i.e. used in another block), then it's not safe to perform

25
test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
View File

@ -3,7 +3,7 @@
; CHECK: _f
; CHECK: adds
; CHECK-NOT: cmp
; CHECK: blxeq _g
; CHECK: blxeq _h
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
@ -12,11 +12,30 @@ entry:
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void (...)* @g(i32 %a, i32 %b) nounwind
tail call void (...)* @h(i32 %a, i32 %b) nounwind
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 %add
}
declare void @g(...)
; CHECK: _g
; CHECK: orrs
; CHECK-NOT: cmp
; CHECK: blxeq _h
define i32 @g(i32 %a, i32 %b) nounwind ssp {
entry:
%add = or i32 %b, %a
%cmp = icmp eq i32 %add, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void (...)* @h(i32 %a, i32 %b) nounwind
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 %add
}
declare void @h(...)