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More dead code elimination in VirtRegMap.
This thing is looking a lot like a virtual register map now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144486 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,7 +19,6 @@
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#define DEBUG_TYPE "virtregmap"
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#include "VirtRegMap.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -32,12 +31,8 @@
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include <algorithm>
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using namespace llvm;
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@ -62,14 +57,7 @@ bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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Virt2StackSlotMap.clear();
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Virt2SplitMap.clear();
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allocatableRCRegs.clear();
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I)
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allocatableRCRegs.insert(std::make_pair(*I,
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TRI->getAllocatableSet(mf, *I)));
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grow();
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return false;
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}
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@ -18,22 +18,14 @@
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#define LLVM_CODEGEN_VIRTREGMAP_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include <map>
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namespace llvm {
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class LiveIntervals;
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class MachineInstr;
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class MachineFunction;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class raw_ostream;
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class SlotIndexes;
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@ -45,18 +37,12 @@ namespace llvm {
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MAX_STACK_SLOT = (1L << 18)-1
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};
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enum ModRef { isRef = 1, isMod = 2, isModRef = 3 };
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typedef std::multimap<MachineInstr*,
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std::pair<unsigned, ModRef> > MI2VirtMapTy;
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private:
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineFunction *MF;
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DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs;
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/// Virt2PhysMap - This is a virtual to physical register
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/// mapping. Each virtual register is required to have an entry in
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/// it; even spilled virtual registers (the register mapped to a
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