mirror of
https://github.com/RPCS3/llvm.git
synced 2024-11-29 22:50:55 +00:00
Mark ARM compare instructions as isCompare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
2d643ef328
commit
0cce3dd326
@ -496,7 +496,7 @@ multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
|
||||
/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
|
||||
/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
|
||||
/// a explicit result, only implicitly set CPSR.
|
||||
let Defs = [CPSR] in {
|
||||
let isCompare = 1, Defs = [CPSR] in {
|
||||
multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
|
||||
bit Commutable = 0> {
|
||||
def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
|
||||
|
Loading…
Reference in New Issue
Block a user