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Match tblegen changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-11-08 20:34:28 +00:00
parent 811731e340
commit 0d53826f36
4 changed files with 51 additions and 40 deletions
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26
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -751,11 +751,14 @@ public:
SDNode *Select(SDOperand Op); SDNode *Select(SDOperand Op);
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base); bool SelectAddrRegImm(SDOperand Op, SDOperand N, SDOperand &Offset,
bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift, SDOperand &Base);
SDOperand &ShiftType); bool SelectAddrMode1(SDOperand Op, SDOperand N, SDOperand &Arg,
bool SelectAddrMode2(SDOperand N, SDOperand &Arg, SDOperand &Offset); SDOperand &Shift, SDOperand &ShiftType);
bool SelectAddrMode5(SDOperand N, SDOperand &Arg, SDOperand &Offset); bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Arg,
SDOperand &Offset);
bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Arg,
SDOperand &Offset);
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc" #include "ARMGenDAGISel.inc"
@ -809,7 +812,8 @@ static bool isRotInt8Immediate(uint32_t x) {
return false; return false;
} }
bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N, bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand Op,
SDOperand N,
SDOperand &Arg, SDOperand &Arg,
SDOperand &Shift, SDOperand &Shift,
SDOperand &ShiftType) { SDOperand &ShiftType) {
@ -853,8 +857,8 @@ bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
return true; return true;
} }
bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand N, SDOperand &Arg, bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
SDOperand &Offset) { SDOperand &Arg, SDOperand &Offset) {
//TODO: complete and cleanup! //TODO: complete and cleanup!
SDOperand Zero = CurDAG->getTargetConstant(0, MVT::i32); SDOperand Zero = CurDAG->getTargetConstant(0, MVT::i32);
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
@ -882,7 +886,8 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand N, SDOperand &Arg,
return true; return true;
} }
bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg, bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op,
SDOperand N, SDOperand &Arg,
SDOperand &Offset) { SDOperand &Offset) {
//TODO: detect offset //TODO: detect offset
Offset = CurDAG->getTargetConstant(0, MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
@ -891,7 +896,8 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg,
} }
//register plus/minus 12 bit offset //register plus/minus 12 bit offset
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset, bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand Op,
SDOperand N, SDOperand &Offset,
SDOperand &Base) { SDOperand &Base) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);

21
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -104,27 +104,31 @@ namespace {
/// SelectAddrImm - Returns true if the address N can be represented by /// SelectAddrImm - Returns true if the address N can be represented by
/// a base register plus a signed 16-bit displacement [r+imm]. /// a base register plus a signed 16-bit displacement [r+imm].
bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base) { bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
SDOperand &Base) {
return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
} }
/// SelectAddrIdx - Given the specified addressed, check to see if it can be /// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can /// represented as an indexed [r+r] operation. Returns false if it can
/// be represented by [r+imm], which are preferred. /// be represented by [r+imm], which are preferred.
bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index) { bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
} }
/// SelectAddrIdxOnly - Given the specified addressed, force it to be /// SelectAddrIdxOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation. /// represented as an indexed [r+r] operation.
bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index) { bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
} }
/// SelectAddrImmShift - Returns true if the address N can be represented by /// SelectAddrImmShift - Returns true if the address N can be represented by
/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
/// for use by STD and friends. /// for use by STD and friends.
bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base) { bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
SDOperand &Base) {
return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG); return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
} }
@ -138,18 +142,18 @@ namespace {
switch (ConstraintCode) { switch (ConstraintCode) {
default: return true; default: return true;
case 'm': // memory case 'm': // memory
if (!SelectAddrIdx(Op, Op0, Op1)) if (!SelectAddrIdx(Op, Op, Op0, Op1))
SelectAddrImm(Op, Op0, Op1); SelectAddrImm(Op, Op, Op0, Op1);
break; break;
case 'o': // offsetable case 'o': // offsetable
if (!SelectAddrImm(Op, Op0, Op1)) { if (!SelectAddrImm(Op, Op, Op0, Op1)) {
Op0 = Op; Op0 = Op;
AddToISelQueue(Op0); // r+0. AddToISelQueue(Op0); // r+0.
Op1 = getSmallIPtrImm(0); Op1 = getSmallIPtrImm(0);
} }
break; break;
case 'v': // not offsetable case 'v': // not offsetable
SelectAddrIdxOnly(Op, Op0, Op1); SelectAddrIdxOnly(Op, Op, Op0, Op1);
break; break;
} }
@ -480,7 +484,6 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
return 0; return 0;
} }
/// SelectCC - Select a comparison of the specified values with the specified /// SelectCC - Select a comparison of the specified values with the specified
/// condition code, returning the CR# of the expression. /// condition code, returning the CR# of the expression.
SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,

13
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -968,8 +968,9 @@ public:
SDNode *Select(SDOperand Op); SDNode *Select(SDOperand Op);
// Complex Pattern Selectors. // Complex Pattern Selectors.
bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Offset);
/// InstructionSelectBasicBlock - This callback is invoked by /// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@ -997,8 +998,8 @@ void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
ScheduleAndEmitDAG(DAG); ScheduleAndEmitDAG(DAG);
} }
bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
SDOperand &Offset) { SDOperand &Base, SDOperand &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
@ -1038,8 +1039,8 @@ bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
return true; return true;
} }
bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
SDOperand &R2) { SDOperand &R1, SDOperand &R2) {
if (Addr.getOpcode() == ISD::FrameIndex) return false; if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::TargetExternalSymbol || if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress) Addr.getOpcode() == ISD::TargetGlobalAddress)

31
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -143,11 +143,11 @@ namespace {
SDNode *Select(SDOperand N); SDNode *Select(SDOperand N);
bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true); bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale, bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index, SDOperand &Disp); SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale, bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index, SDOperand &Disp); SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
bool SelectScalarSSELoad(SDOperand Root, SDOperand Pred, bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
SDOperand N, SDOperand &Base, SDOperand &Scale, SDOperand N, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp, SDOperand &Index, SDOperand &Disp,
SDOperand &InChain, SDOperand &OutChain); SDOperand &InChain, SDOperand &OutChain);
@ -773,8 +773,9 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
/// SelectAddr - returns true if it is able pattern match an addressing mode. /// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can /// It returns the operands which make up the maximal addressing mode it can
/// match by reference. /// match by reference.
bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale, bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index, SDOperand &Disp) { SDOperand &Scale, SDOperand &Index,
SDOperand &Disp) {
X86ISelAddressMode AM; X86ISelAddressMode AM;
if (MatchAddress(N, AM)) if (MatchAddress(N, AM))
return false; return false;
@ -805,7 +806,7 @@ static inline bool isZeroNode(SDOperand Elt) {
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor /// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64. /// is derived from the type of N, which is either v4f32 or v2f64.
bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Root, SDOperand Pred, bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
SDOperand N, SDOperand &Base, SDOperand N, SDOperand &Base,
SDOperand &Scale, SDOperand &Index, SDOperand &Scale, SDOperand &Index,
SDOperand &Disp, SDOperand &InChain, SDOperand &Disp, SDOperand &InChain,
@ -814,9 +815,9 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Root, SDOperand Pred,
InChain = N.getOperand(0).getValue(1); InChain = N.getOperand(0).getValue(1);
if (ISD::isNON_EXTLoad(InChain.Val) && if (ISD::isNON_EXTLoad(InChain.Val) &&
InChain.getValue(0).hasOneUse() && InChain.getValue(0).hasOneUse() &&
CanBeFoldedBy(N.Val, Pred.Val, Root.Val)) { CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(InChain); LoadSDNode *LD = cast<LoadSDNode>(InChain);
if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp)) if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
return false; return false;
OutChain = LD->getChain(); OutChain = LD->getChain();
return true; return true;
@ -856,7 +857,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Root, SDOperand Pred,
// Okay, this is a zero extending load. Fold it. // Okay, this is a zero extending load. Fold it.
LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(1).getOperand(0)); LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(1).getOperand(0));
if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp)) if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
return false; return false;
OutChain = LD->getChain(); OutChain = LD->getChain();
InChain = SDOperand(LD, 1); InChain = SDOperand(LD, 1);
@ -869,8 +870,8 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Root, SDOperand Pred,
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
/// mode it matches can be cost effectively emitted as an LEA instruction. /// mode it matches can be cost effectively emitted as an LEA instruction.
bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base, bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
SDOperand &Scale, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp) { SDOperand &Index, SDOperand &Disp) {
X86ISelAddressMode AM; X86ISelAddressMode AM;
if (MatchAddress(N, AM)) if (MatchAddress(N, AM))
@ -927,7 +928,7 @@ bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
if (ISD::isNON_EXTLoad(N.Val) && if (ISD::isNON_EXTLoad(N.Val) &&
N.hasOneUse() && N.hasOneUse() &&
CanBeFoldedBy(N.Val, P.Val, P.Val)) CanBeFoldedBy(N.Val, P.Val, P.Val))
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp); return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
return false; return false;
} }
@ -1288,7 +1289,7 @@ SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
case 'v': // not offsetable ?? case 'v': // not offsetable ??
default: return true; default: return true;
case 'm': // memory case 'm': // memory
if (!SelectAddr(Op, Op0, Op1, Op2, Op3)) if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
return true; return true;
break; break;
} }