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Convert DOUT to DEBUG(errs()...).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79753 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2009-08-22 20:23:49 +00:00
parent 8e6179fb13
commit 0d6b1b1248
1 changed files with 27 additions and 30 deletions
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57
lib/CodeGen/LowerSubregs.cpp
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@ -121,7 +121,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
"Extract destination must be in a physical register"); "Extract destination must be in a physical register");
assert(SrcReg && "invalid subregister index for register"); assert(SrcReg && "invalid subregister index for register");
DOUT << "subreg: CONVERTING: " << *MI; DEBUG(errs() << "subreg: CONVERTING: " << *MI);
if (SrcReg == DstReg) { if (SrcReg == DstReg) {
// No need to insert an identity copy instruction. // No need to insert an identity copy instruction.
@ -130,10 +130,11 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
// instruction with IMPLICIT_DEF. // instruction with IMPLICIT_DEF.
MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF)); MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF));
MI->RemoveOperand(2); // SubIdx MI->RemoveOperand(2); // SubIdx
DOUT << "subreg: replace by: " << *MI; DEBUG(errs() << "subreg: replace by: " << *MI);
return true; return true;
} }
DOUT << "subreg: eliminated!";
DEBUG(errs() << "subreg: eliminated!");
} else { } else {
// Insert copy // Insert copy
const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg); const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
@ -146,14 +147,13 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
TransferDeadFlag(MI, DstReg, TRI); TransferDeadFlag(MI, DstReg, TRI);
if (MI->getOperand(1).isKill()) if (MI->getOperand(1).isKill())
TransferKillFlag(MI, SuperReg, TRI, true); TransferKillFlag(MI, SuperReg, TRI, true);
DEBUG({
#ifndef NDEBUG MachineBasicBlock::iterator dMI = MI;
MachineBasicBlock::iterator dMI = MI; errs() << "subreg: " << *(--dMI);
DOUT << "subreg: " << *(--dMI); });
#endif
} }
DOUT << "\n"; DEBUG(errs() << '\n');
MBB->erase(MI); MBB->erase(MI);
return true; return true;
} }
@ -181,7 +181,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
"Inserted value must be in a physical register"); "Inserted value must be in a physical register");
DOUT << "subreg: CONVERTING: " << *MI; DEBUG(errs() << "subreg: CONVERTING: " << *MI);
if (DstSubReg == InsReg && InsSIdx == 0) { if (DstSubReg == InsReg && InsSIdx == 0) {
// No need to insert an identify copy instruction. // No need to insert an identify copy instruction.
@ -190,7 +190,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
// %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
// The first def is defining RAX, not EAX so the top bits were not // The first def is defining RAX, not EAX so the top bits were not
// zero extended. // zero extended.
DOUT << "subreg: eliminated!"; DEBUG(errs() << "subreg: eliminated!");
} else { } else {
// Insert sub-register copy // Insert sub-register copy
const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
@ -201,14 +201,13 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
TransferDeadFlag(MI, DstSubReg, TRI); TransferDeadFlag(MI, DstSubReg, TRI);
if (MI->getOperand(2).isKill()) if (MI->getOperand(2).isKill())
TransferKillFlag(MI, InsReg, TRI); TransferKillFlag(MI, InsReg, TRI);
DEBUG({
#ifndef NDEBUG MachineBasicBlock::iterator dMI = MI;
MachineBasicBlock::iterator dMI = MI; errs() << "subreg: " << *(--dMI);
DOUT << "subreg: " << *(--dMI); });
#endif
} }
DOUT << "\n"; DEBUG(errs() << '\n');
MBB->erase(MI); MBB->erase(MI);
return true; return true;
} }
@ -239,7 +238,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
"Inserted value must be in a physical register"); "Inserted value must be in a physical register");
DOUT << "subreg: CONVERTING: " << *MI; DEBUG(errs() << "subreg: CONVERTING: " << *MI);
if (DstSubReg == InsReg) { if (DstSubReg == InsReg) {
// No need to insert an identity copy instruction. If the SrcReg was // No need to insert an identity copy instruction. If the SrcReg was
@ -252,7 +251,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
else else
MIB.addReg(InsReg, RegState::ImplicitKill); MIB.addReg(InsReg, RegState::ImplicitKill);
} else { } else {
DOUT << "subreg: eliminated!\n"; DEBUG(errs() << "subreg: eliminated!\n");
MBB->erase(MI); MBB->erase(MI);
return true; return true;
} }
@ -287,12 +286,11 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
TransferKillFlag(MI, InsReg, TRI); TransferKillFlag(MI, InsReg, TRI);
} }
#ifndef NDEBUG DEBUG({
MachineBasicBlock::iterator dMI = MI; MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI); errs() << "subreg: " << *(--dMI) << "\n";
#endif });
DOUT << "\n";
MBB->erase(MI); MBB->erase(MI);
return true; return true;
} }
@ -301,13 +299,12 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
/// copies. /// copies.
/// ///
bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) { bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DOUT << "Machine Function\n"; DEBUG(errs() << "Machine Function\n"
<< "********** LOWERING SUBREG INSTRS **********\n"
bool MadeChange = false; << "********** Function: "
<< MF.getFunction()->getName() << '\n');
DOUT << "********** LOWERING SUBREG INSTRS **********\n"; bool MadeChange = false;
DEBUG(errs() << "********** Function: "
<< MF.getFunction()->getName() << '\n');
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) { mbbi != mbbe; ++mbbi) {