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[DAGCombiner] Allow visitEXTRACT_SUBVECTOR to combine with BUILD_VECTORS between LegalizeVectorOps and LegalizeDAG.
BUILD_VECTORs aren't themselves legalized until LegalizeDAG so we should still be able to create an "illegal" one before that. This helps combine with BUILD_VECTORS that are introduced during LegalizeVectorOps due to unrolling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327446 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
fc9466dd05
commit
0d74daca01
@ -15477,7 +15477,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
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unsigned NumElems = ExtractSize / EltSize;
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EVT ExtractVT = EVT::getVectorVT(*DAG.getContext(),
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InVT.getVectorElementType(), NumElems);
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if ((!LegalOperations ||
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if ((Level < AfterLegalizeDAG ||
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TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT)) &&
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(!LegalTypes || TLI.isTypeLegal(ExtractVT))) {
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unsigned IdxVal = (Idx->getZExtValue() * NVT.getScalarSizeInBits()) /
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@ -1380,13 +1380,12 @@ define <16 x i32> @f16xi32_i128(<16 x i32> %a) {
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define <4 x i64> @f4xi64_i128(<4 x i64> %a) {
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; AVX-LABEL: f4xi64_i128:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [0,0,1,0,0,0,1,0]
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; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX-NEXT: vpaddq %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vpaddq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,0,1,0]
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; AVX-NEXT: vpaddq %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpaddq %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0
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; AVX-NEXT: retl
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;
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; ALL32-LABEL: f4xi64_i128:
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@ -1424,16 +1423,16 @@ define <4 x i64> @f4xi64_i128(<4 x i64> %a) {
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define <8 x i64> @f8xi64_i128(<8 x i64> %a) {
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; AVX-LABEL: f8xi64_i128:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [0,0,1,0,0,0,1,0]
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; AVX-NEXT: vextractf128 $1, %ymm2, %xmm3
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; AVX-NEXT: vextractf128 $1, %ymm1, %xmm4
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; AVX-NEXT: vpaddq %xmm3, %xmm4, %xmm4
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; AVX-NEXT: vpaddq %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm4
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; AVX-NEXT: vpaddq %xmm3, %xmm4, %xmm3
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; AVX-NEXT: vpaddq %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
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; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [0,0,1,0]
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; AVX-NEXT: vpaddq %xmm3, %xmm2, %xmm2
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; AVX-NEXT: vpaddq %xmm3, %xmm1, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX-NEXT: vpaddq %xmm3, %xmm2, %xmm2
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; AVX-NEXT: vpaddq %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,1,0,0,0,1,0]
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; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX-NEXT: retl
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@ -1499,16 +1498,17 @@ define <8 x i64> @f8xi64_i128(<8 x i64> %a) {
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define <8 x i64> @f8xi64_i256(<8 x i64> %a) {
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; AVX-LABEL: f8xi64_i256:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqa {{.*#+}} ymm2 = [0,0,1,0,2,0,3,0]
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; AVX-NEXT: vextractf128 $1, %ymm2, %xmm3
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; AVX-NEXT: vextractf128 $1, %ymm1, %xmm4
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; AVX-NEXT: vpaddq %xmm3, %xmm4, %xmm4
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; AVX-NEXT: vpaddq %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm4
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; AVX-NEXT: vpaddq %xmm3, %xmm4, %xmm3
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; AVX-NEXT: vpaddq %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
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; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [2,0,3,0]
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; AVX-NEXT: vpaddq %xmm3, %xmm2, %xmm2
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; AVX-NEXT: vmovdqa {{.*#+}} xmm4 = [0,0,1,0]
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; AVX-NEXT: vpaddq %xmm4, %xmm1, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX-NEXT: vpaddq %xmm3, %xmm2, %xmm2
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; AVX-NEXT: vpaddq %xmm4, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,1,0,2,0,3,0]
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; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX-NEXT: retl
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@ -28,19 +28,9 @@ define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext
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; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movswl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovd %eax, %xmm0
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; X32-NEXT: sarl $31, %eax
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; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
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; X32-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
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; X32-NEXT: sarl $31, %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: vmovd %eax, %xmm1
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; X32-NEXT: sarl $31, %eax
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; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
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; X32-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; X32-NEXT: sarl $31, %edx
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; X32-NEXT: vpinsrd $3, %edx, %xmm1, %xmm1
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; X32-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
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; X32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
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; X32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X32-NEXT: retl
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@ -391,19 +381,17 @@ define <4 x float> @signbits_ashr_sext_select_shuffle_sitofp(<4 x i64> %a0, <4 x
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: andl $-16, %esp
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; X32-NEXT: subl $16, %esp
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; X32-NEXT: vmovdqa {{.*#+}} ymm3 = [33,0,63,0,33,0,63,0]
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; X32-NEXT: vextractf128 $1, %ymm3, %xmm4
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; X32-NEXT: vmovdqa {{.*#+}} xmm5 = [0,2147483648,0,2147483648]
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; X32-NEXT: vpsrlq %xmm4, %xmm5, %xmm6
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; X32-NEXT: vextractf128 $1, %ymm2, %xmm7
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; X32-NEXT: vpsrlq %xmm4, %xmm7, %xmm4
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; X32-NEXT: vpxor %xmm6, %xmm4, %xmm4
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; X32-NEXT: vpsubq %xmm6, %xmm4, %xmm4
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; X32-NEXT: vmovdqa {{.*#+}} xmm3 = [33,0,63,0]
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; X32-NEXT: vmovdqa {{.*#+}} xmm4 = [0,2147483648,0,2147483648]
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; X32-NEXT: vpsrlq %xmm3, %xmm4, %xmm4
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; X32-NEXT: vextractf128 $1, %ymm2, %xmm5
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; X32-NEXT: vpsrlq %xmm3, %xmm5, %xmm5
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; X32-NEXT: vpxor %xmm4, %xmm5, %xmm5
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; X32-NEXT: vpsubq %xmm4, %xmm5, %xmm5
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; X32-NEXT: vpsrlq %xmm3, %xmm2, %xmm2
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; X32-NEXT: vpxor %xmm5, %xmm2, %xmm2
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; X32-NEXT: vpsubq %xmm5, %xmm2, %xmm2
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; X32-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2
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; X32-NEXT: vpxor %xmm4, %xmm2, %xmm2
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; X32-NEXT: vpsubq %xmm4, %xmm2, %xmm2
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; X32-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2
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; X32-NEXT: vpmovsxdq 8(%ebp), %xmm3
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; X32-NEXT: vpmovsxdq 16(%ebp), %xmm4
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; X32-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
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@ -2227,67 +2227,89 @@ define void @PR34947() {
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;
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; X86-AVX1-LABEL: PR34947:
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; X86-AVX1: # %bb.0:
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; X86-AVX1-NEXT: pushl %esi
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; X86-AVX1-NEXT: pushl %ebp
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
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; X86-AVX1-NEXT: .cfi_offset %esi, -8
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; X86-AVX1-NEXT: pushl %ebx
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 12
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; X86-AVX1-NEXT: pushl %edi
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 16
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; X86-AVX1-NEXT: pushl %esi
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 20
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; X86-AVX1-NEXT: subl $16, %esp
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; X86-AVX1-NEXT: .cfi_def_cfa_offset 36
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; X86-AVX1-NEXT: .cfi_offset %esi, -20
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; X86-AVX1-NEXT: .cfi_offset %edi, -16
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; X86-AVX1-NEXT: .cfi_offset %ebx, -12
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; X86-AVX1-NEXT: .cfi_offset %ebp, -8
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; X86-AVX1-NEXT: vmovdqa (%eax), %ymm0
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; X86-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, %ecx
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; X86-AVX1-NEXT: vmovd %xmm0, %esi
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %esi
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; X86-AVX1-NEXT: vmovd %edx, %xmm1
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; X86-AVX1-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: vpinsrd $3, %edx, %xmm1, %xmm1
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; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; X86-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, %ecx
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; X86-AVX1-NEXT: vmovd %xmm0, %esi
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %esi
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; X86-AVX1-NEXT: vmovd %edx, %xmm2
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; X86-AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl (%eax)
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; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [8199,8199,8199,8199]
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; X86-AVX1-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
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; X86-AVX1-NEXT: vpmaddwd %xmm2, %xmm1, %xmm1
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; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; X86-AVX1-NEXT: vmovd %edx, %xmm1
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; X86-AVX1-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, (%esp) # 4-byte Spill
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; X86-AVX1-NEXT: vmovd %xmm0, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, %ebp
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; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
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; X86-AVX1-NEXT: divl %ecx
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; X86-AVX1-NEXT: movl %edx, %ecx
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vpextrd $2, %xmm0, %esi
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; X86-AVX1-NEXT: divl %esi
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; X86-AVX1-NEXT: movl %edx, %esi
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vpextrd $1, %xmm0, %edi
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; X86-AVX1-NEXT: divl %edi
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; X86-AVX1-NEXT: movl %edx, %edi
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; X86-AVX1-NEXT: xorl %eax, %eax
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; X86-AVX1-NEXT: xorl %edx, %edx
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; X86-AVX1-NEXT: vmovd %xmm0, %ebx
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; X86-AVX1-NEXT: divl %ebx
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; X86-AVX1-NEXT: vmovd %edx, %xmm0
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; X86-AVX1-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
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; X86-AVX1-NEXT: vpinsrd $2, %esi, %xmm0, %xmm0
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; X86-AVX1-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
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; X86-AVX1-NEXT: vmovd %ebp, %xmm1
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; X86-AVX1-NEXT: vpinsrd $1, (%esp), %xmm1, %xmm1 # 4-byte Folded Reload
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; X86-AVX1-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1 # 4-byte Folded Reload
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; X86-AVX1-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1 # 4-byte Folded Reload
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; X86-AVX1-NEXT: vmovd {{[0-9]+}}(%esp), %xmm2 # 4-byte Folded Reload
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; X86-AVX1-NEXT: # xmm2 = mem[0],zero,zero,zero
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; X86-AVX1-NEXT: movl $8199, %eax # imm = 0x2007
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; X86-AVX1-NEXT: vmovd %eax, %xmm2
|
||||
; X86-AVX1-NEXT: vpmulld %xmm2, %xmm1, %xmm1
|
||||
; X86-AVX1-NEXT: vmovd %eax, %xmm3
|
||||
; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [8199,8199,8199,8199]
|
||||
; X86-AVX1-NEXT: vpmaddwd %xmm4, %xmm0, %xmm0
|
||||
; X86-AVX1-NEXT: vpmaddwd %xmm4, %xmm1, %xmm1
|
||||
; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; X86-AVX1-NEXT: vpmulld %xmm3, %xmm2, %xmm1
|
||||
; X86-AVX1-NEXT: vmovd %xmm1, (%eax)
|
||||
; X86-AVX1-NEXT: vmovaps %ymm0, (%eax)
|
||||
; X86-AVX1-NEXT: addl $16, %esp
|
||||
; X86-AVX1-NEXT: popl %esi
|
||||
; X86-AVX1-NEXT: popl %edi
|
||||
; X86-AVX1-NEXT: popl %ebx
|
||||
; X86-AVX1-NEXT: popl %ebp
|
||||
; X86-AVX1-NEXT: vzeroupper
|
||||
; X86-AVX1-NEXT: retl
|
||||
;
|
||||
@ -2399,63 +2421,77 @@ define void @PR34947() {
|
||||
;
|
||||
; X64-AVX1-LABEL: PR34947:
|
||||
; X64-AVX1: # %bb.0:
|
||||
; X64-AVX1-NEXT: pushq %rbp
|
||||
; X64-AVX1-NEXT: .cfi_def_cfa_offset 16
|
||||
; X64-AVX1-NEXT: pushq %rbx
|
||||
; X64-AVX1-NEXT: .cfi_def_cfa_offset 24
|
||||
; X64-AVX1-NEXT: .cfi_offset %rbx, -24
|
||||
; X64-AVX1-NEXT: .cfi_offset %rbp, -16
|
||||
; X64-AVX1-NEXT: vmovdqa (%rax), %ymm0
|
||||
; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %ecx
|
||||
; X64-AVX1-NEXT: vmovd %xmm0, %esi
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %esi
|
||||
; X64-AVX1-NEXT: vmovd %edx, %xmm1
|
||||
; X64-AVX1-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
|
||||
; X64-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
|
||||
; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: vpinsrd $3, %edx, %xmm1, %xmm1
|
||||
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %ecx
|
||||
; X64-AVX1-NEXT: vmovd %xmm0, %esi
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %esi
|
||||
; X64-AVX1-NEXT: vmovd %edx, %xmm2
|
||||
; X64-AVX1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
|
||||
; X64-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
|
||||
; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl (%rax)
|
||||
; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [8199,8199,8199,8199]
|
||||
; X64-AVX1-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
|
||||
; X64-AVX1-NEXT: vpmaddwd %xmm2, %xmm1, %xmm1
|
||||
; X64-AVX1-NEXT: movl %edx, %r8d
|
||||
; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %r9d
|
||||
; X64-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %r10d
|
||||
; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %r11d
|
||||
; X64-AVX1-NEXT: vmovd %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %esi
|
||||
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; X64-AVX1-NEXT: vpextrd $3, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %edi
|
||||
; X64-AVX1-NEXT: vpextrd $2, %xmm0, %ecx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ecx
|
||||
; X64-AVX1-NEXT: movl %edx, %ecx
|
||||
; X64-AVX1-NEXT: vpextrd $1, %xmm0, %ebx
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ebx
|
||||
; X64-AVX1-NEXT: movl %edx, %ebx
|
||||
; X64-AVX1-NEXT: vmovd %xmm0, %ebp
|
||||
; X64-AVX1-NEXT: xorl %eax, %eax
|
||||
; X64-AVX1-NEXT: xorl %edx, %edx
|
||||
; X64-AVX1-NEXT: divl %ebp
|
||||
; X64-AVX1-NEXT: vmovd %edx, %xmm0
|
||||
; X64-AVX1-NEXT: vpinsrd $1, %ebx, %xmm0, %xmm0
|
||||
; X64-AVX1-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
|
||||
; X64-AVX1-NEXT: vpinsrd $3, %edi, %xmm0, %xmm0
|
||||
; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [8199,8199,8199,8199]
|
||||
; X64-AVX1-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0
|
||||
; X64-AVX1-NEXT: vmovd %esi, %xmm2
|
||||
; X64-AVX1-NEXT: vpinsrd $1, %r11d, %xmm2, %xmm2
|
||||
; X64-AVX1-NEXT: vpinsrd $2, %r10d, %xmm2, %xmm2
|
||||
; X64-AVX1-NEXT: vpinsrd $3, %r9d, %xmm2, %xmm2
|
||||
; X64-AVX1-NEXT: vpmaddwd %xmm1, %xmm2, %xmm1
|
||||
; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; X64-AVX1-NEXT: vmovd %edx, %xmm1
|
||||
; X64-AVX1-NEXT: vmovd %r8d, %xmm1
|
||||
; X64-AVX1-NEXT: movl $8199, %eax # imm = 0x2007
|
||||
; X64-AVX1-NEXT: vmovd %eax, %xmm2
|
||||
; X64-AVX1-NEXT: vpmulld %xmm2, %xmm1, %xmm1
|
||||
; X64-AVX1-NEXT: vmovd %xmm1, (%rax)
|
||||
; X64-AVX1-NEXT: vmovaps %ymm0, (%rax)
|
||||
; X64-AVX1-NEXT: popq %rbx
|
||||
; X64-AVX1-NEXT: popq %rbp
|
||||
; X64-AVX1-NEXT: vzeroupper
|
||||
; X64-AVX1-NEXT: retq
|
||||
;
|
||||
|
||||
@ -916,21 +916,22 @@ define void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64> %b) {
|
||||
; X32-AVX1-LABEL: fallback_broadcast_v4i64_to_v8i64:
|
||||
; X32-AVX1: # %bb.0: # %entry
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} ymm4 = [1,0,2,0,3,0,4,0]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5
|
||||
; X32-AVX1-NEXT: vpaddq %xmm5, %xmm3, %xmm3
|
||||
; X32-AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [3,0,4,0]
|
||||
; X32-AVX1-NEXT: vpaddq %xmm4, %xmm3, %xmm3
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [1,0,2,0]
|
||||
; X32-AVX1-NEXT: vpaddq %xmm5, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
|
||||
; X32-AVX1-NEXT: vpaddq %xmm5, %xmm3, %xmm3
|
||||
; X32-AVX1-NEXT: vpaddq %xmm4, %xmm2, %xmm2
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; X32-AVX1-NEXT: vpaddq %xmm5, %xmm3, %xmm3
|
||||
; X32-AVX1-NEXT: vpaddq %xmm4, %xmm1, %xmm1
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
|
||||
; X32-AVX1-NEXT: vandps %ymm4, %ymm1, %ymm1
|
||||
; X32-AVX1-NEXT: vandps %ymm4, %ymm2, %ymm2
|
||||
; X32-AVX1-NEXT: vmovaps {{.*#+}} ymm3 = [1,0,2,0,3,0,4,0]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
|
||||
; X32-AVX1-NEXT: vpaddq %xmm4, %xmm6, %xmm6
|
||||
; X32-AVX1-NEXT: vpaddq %xmm5, %xmm2, %xmm2
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm2, %ymm2
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm6
|
||||
; X32-AVX1-NEXT: vpaddq %xmm4, %xmm6, %xmm4
|
||||
; X32-AVX1-NEXT: vpaddq %xmm5, %xmm1, %xmm1
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1
|
||||
; X32-AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1
|
||||
; X32-AVX1-NEXT: vandps %ymm3, %ymm2, %ymm2
|
||||
; X32-AVX1-NEXT: vmovups %ymm0, ga4
|
||||
; X32-AVX1-NEXT: vmovups %ymm2, gb4+32
|
||||
; X32-AVX1-NEXT: vmovups %ymm1, gb4
|
||||
|
||||
@ -1183,29 +1183,29 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
;
|
||||
; X32-AVX1-LABEL: constant_shift_v4i64:
|
||||
; X32-AVX1: # %bb.0:
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} ymm1 = [1,0,7,0,31,0,62,0]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,2147483648,0,2147483648]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm2, %xmm3, %xmm4
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm5, %xmm3, %xmm6
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm6[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm6
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm2, %xmm6, %xmm2
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm5, %xmm6, %xmm5
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm5[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2
|
||||
; X32-AVX1-NEXT: vpsubq %xmm4, %xmm2, %xmm2
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm3, %xmm4
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm1[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm5, %xmm3, %xmm3
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm4[0,1,2,3],xmm3[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm1
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm5, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpsubq %xmm3, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [31,0,62,0]
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm2, %xmm3
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm4, %xmm2, %xmm5
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm5[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm4, %xmm5, %xmm4
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm5, %xmm1
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm1
|
||||
; X32-AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm1
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,0,7,0]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm3, %xmm2, %xmm4
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm3[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm5, %xmm2, %xmm2
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm5, %xmm0, %xmm4
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm3, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm4[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; X32-AVX1-NEXT: retl
|
||||
;
|
||||
; X32-AVX2-LABEL: constant_shift_v4i64:
|
||||
|
||||
@ -930,18 +930,18 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
;
|
||||
; X32-AVX1-LABEL: constant_shift_v4i64:
|
||||
; X32-AVX1: # %bb.0:
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} ymm1 = [1,0,7,0,31,0,62,0]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [31,0,62,0]
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm2, %xmm3, %xmm4
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm2, %xmm3, %xmm2
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm3
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm3, %xmm1
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,0,7,0]
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm3, %xmm0, %xmm3
|
||||
; X32-AVX1-NEXT: vpsrlq %xmm2, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; X32-AVX1-NEXT: retl
|
||||
;
|
||||
; X32-AVX2-LABEL: constant_shift_v4i64:
|
||||
|
||||
@ -857,18 +857,18 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
;
|
||||
; X32-AVX1-LABEL: constant_shift_v4i64:
|
||||
; X32-AVX1: # %bb.0:
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} ymm1 = [1,0,7,0,31,0,62,0]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [31,0,62,0]
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; X32-AVX1-NEXT: vpsllq %xmm2, %xmm3, %xmm4
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsllq %xmm2, %xmm3, %xmm2
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm3
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; X32-AVX1-NEXT: vpsllq %xmm1, %xmm3, %xmm1
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,0,7,0]
|
||||
; X32-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,3,0,1]
|
||||
; X32-AVX1-NEXT: vpsllq %xmm3, %xmm0, %xmm3
|
||||
; X32-AVX1-NEXT: vpsllq %xmm2, %xmm0, %xmm0
|
||||
; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
|
||||
; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; X32-AVX1-NEXT: retl
|
||||
;
|
||||
; X32-AVX2-LABEL: constant_shift_v4i64:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user