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[PowerPC] Fix PR22711 - Misaligned .toc section

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Straightforward patch to emit an alignment directive when emitting a
TOC entry.  The test case was generated from the test in PR22711 that
demonstrated a misaligned .toc section.  The object code is run
through llvm-readobj to verify that the correct alignment has been
applied to the .toc section.

Thanks to Ulrich Weigand for running down where the fix was needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230801 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt 2015-02-27 22:14:10 +00:00
parent 9f9dcf8046
commit 0e1e8e2f62
2 changed files with 66 additions and 0 deletions
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1
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -145,6 +145,7 @@ public:
} }
void emitTCEntry(const MCSymbol &S) override { void emitTCEntry(const MCSymbol &S) override {
// Creates a R_PPC64_TOC relocation // Creates a R_PPC64_TOC relocation
Streamer.EmitValueToAlignment(8);
Streamer.EmitSymbolValue(&S, 8); Streamer.EmitSymbolValue(&S, 8);
} }
void emitMachine(StringRef CPU) override { void emitMachine(StringRef CPU) override {

65
test/CodeGen/PowerPC/pr22711.ll Normal file
View File

@ -0,0 +1,65 @@
; Verify that the .toc section is aligned on an 8-byte boundary.
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -filetype=obj -o - | llvm-readobj --sections | FileCheck %s
define void @test(i32* %a) {
entry:
%a.addr = alloca i32*, align 8
store i32* %a, i32** %a.addr, align 8
%0 = load i32** %a.addr, align 8
%incdec.ptr = getelementptr inbounds i32* %0, i32 1
store i32* %incdec.ptr, i32** %a.addr, align 8
%1 = load i32* %0, align 4
switch i32 %1, label %sw.epilog [
i32 17, label %sw.bb
i32 13, label %sw.bb1
i32 11, label %sw.bb2
i32 7, label %sw.bb3
i32 5, label %sw.bb4
i32 3, label %sw.bb5
i32 2, label %sw.bb6
]
sw.bb: ; preds = %entry
%2 = load i32** %a.addr, align 8
store i32 2, i32* %2, align 4
br label %sw.epilog
sw.bb1: ; preds = %entry
%3 = load i32** %a.addr, align 8
store i32 3, i32* %3, align 4
br label %sw.epilog
sw.bb2: ; preds = %entry
%4 = load i32** %a.addr, align 8
store i32 5, i32* %4, align 4
br label %sw.epilog
sw.bb3: ; preds = %entry
%5 = load i32** %a.addr, align 8
store i32 7, i32* %5, align 4
br label %sw.epilog
sw.bb4: ; preds = %entry
%6 = load i32** %a.addr, align 8
store i32 11, i32* %6, align 4
br label %sw.epilog
sw.bb5: ; preds = %entry
%7 = load i32** %a.addr, align 8
store i32 13, i32* %7, align 4
br label %sw.epilog
sw.bb6: ; preds = %entry
%8 = load i32** %a.addr, align 8
store i32 17, i32* %8, align 4
br label %sw.epilog
sw.epilog: ; preds = %entry, %sw.bb6, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
ret void
}
; CHECK: Name: .toc
; CHECK: AddressAlignment: 8
; CHECK: Name: .rela.toc