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Allow FP arguments pass / return
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76015 91177308-0d34-0410-b5e6-96231b3b80d8
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2c97ae8826
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0e31d5cf80
lib/Target/SystemZ
@ -17,7 +17,11 @@ def RetCC_SystemZ : CallingConv<[
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// i64 is returned in register R2
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CCIfType<[i64], CCAssignToReg<[R2D]>>
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CCIfType<[i64], CCAssignToReg<[R2D]>>,
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// f32 / f64 are returned in F0
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CCIfType<[f32], CCAssignToReg<[F0S]>>,
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CCIfType<[f64], CCAssignToReg<[F0L]>>
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]>;
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//===----------------------------------------------------------------------===//
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@ -31,6 +35,11 @@ def CC_SystemZ : CallingConv<[
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// integer registers.
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CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>,
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// The first 4 ifloating point arguments of non-varargs functions are passed
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// in FP registers.
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CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
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CCIfType<[f64], CCAssignToReg<[F0L, F2L, F4L, F6L]>>,
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// Integer values get stored in stack slots that are 8 bytes in
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// size and 8-byte aligned.
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CCIfType<[i64], CCAssignToStack<8, 8>>
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@ -173,33 +173,42 @@ SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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MVT RegVT = VA.getLocVT();
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TargetRegisterClass *RC;
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switch (RegVT.getSimpleVT()) {
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default:
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cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
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<< RegVT.getSimpleVT()
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<< "\n";
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abort();
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case MVT::i64:
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unsigned VReg =
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RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
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// If this is an 8/16/32-bit value, it is really passed promoted to 64
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
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ArgValues.push_back(ArgValue);
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case MVT::i64:
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RC = SystemZ::GR64RegisterClass;
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break;
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case MVT::f32:
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RC = SystemZ::FP32RegisterClass;
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break;
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case MVT::f64:
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RC = SystemZ::FP64RegisterClass;
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break;
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}
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unsigned VReg = RegInfo.createVirtualRegister(RC);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
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// If this is an 8/16/32-bit value, it is really passed promoted to 64
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
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ArgValues.push_back(ArgValue);
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} else {
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// Sanity check
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assert(VA.isMemLoc());
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