RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-24 04:56:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mips] Added FPXX modeless calling convention.

Browse Source 
Differential Revision: http://reviews.llvm.org/D4293


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212726 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-07-10 15:36:12 +00:00
parent a9af0558b2
commit 0ef47114d3
7 changed files with 100 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/Mips/Mips.td
View File

@ -61,6 +61,8 @@ def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
"Support 64-bit FP registers.">;
def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
"Support for FPXX.">;
def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
"IEEE 754-2008 NaN encoding.">;
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",

5
lib/Target/Mips/MipsCallingConv.td
View File

@ -239,6 +239,11 @@ def RetCC_Mips : CallingConv<[
def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
(sequence "S%u", 7, 0))>;
def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
(sequence "S%u", 7, 0))> {
let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
}
def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
(sequence "S%u", 7, 0))>;

6
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -93,6 +93,9 @@ MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
if (Subtarget.isFP64bit())
return CSR_O32_FP64_SaveList;
if (Subtarget.isFPXX())
return CSR_O32_FPXX_SaveList;
return CSR_O32_SaveList;
}
@ -110,6 +113,9 @@ MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
if (Subtarget.isFP64bit())
return CSR_O32_FP64_RegMask;
if (Subtarget.isFPXX())
return CSR_O32_FPXX_RegMask;
return CSR_O32_RegMask;
}

2
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -107,7 +107,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
Reloc::Model _RM, MipsTargetMachine *_TM)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true),
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),

4
lib/Target/Mips/MipsSubtarget.h
View File

@ -62,6 +62,9 @@ protected:
// floating point registers instead of only using even ones.
bool IsSingleFloat;
// IsFPXX - MIPS O32 modeless ABI.
bool IsFPXX;
// IsFP64bit - The target processor has 64-bit floating point registers.
bool IsFP64bit;
@ -206,6 +209,7 @@ public:
bool hasCnMips() const { return HasCnMips; }
bool isLittle() const { return IsLittle; }
bool isFPXX() const { return IsFPXX; }
bool isFP64bit() const { return IsFP64bit; }
bool useOddSPReg() const { return UseOddSPReg; }
bool isNaN2008() const { return IsNaN2008bit; }

58
test/CodeGen/Mips/cconv/callee-saved-fpxx.ll Normal file
View File

@ -0,0 +1,58 @@
; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s
; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s
; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV %s
; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV %s
; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s
; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s
; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV --check-prefix=O32-FPXX-INV %s
; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV --check-prefix=O32-FPXX-INV %s
define void @fpu_clobber() nounwind {
entry:
call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
ret void
}
; O32-FPXX-LABEL: fpu_clobber:
; O32-FPXX-INV-NOT: sdc1 $f0,
; O32-FPXX-INV-NOT: sdc1 $f1,
; O32-FPXX-INV-NOT: sdc1 $f2,
; O32-FPXX-INV-NOT: sdc1 $f3,
; O32-FPXX-INV-NOT: sdc1 $f4,
; O32-FPXX-INV-NOT: sdc1 $f5,
; O32-FPXX-INV-NOT: sdc1 $f6,
; O32-FPXX-INV-NOT: sdc1 $f7,
; O32-FPXX-INV-NOT: sdc1 $f8,
; O32-FPXX-INV-NOT: sdc1 $f9,
; O32-FPXX-INV-NOT: sdc1 $f10,
; O32-FPXX-INV-NOT: sdc1 $f11,
; O32-FPXX-INV-NOT: sdc1 $f12,
; O32-FPXX-INV-NOT: sdc1 $f13,
; O32-FPXX-INV-NOT: sdc1 $f14,
; O32-FPXX-INV-NOT: sdc1 $f15,
; O32-FPXX-INV-NOT: sdc1 $f16,
; O32-FPXX-INV-NOT: sdc1 $f17,
; O32-FPXX-INV-NOT: sdc1 $f18,
; O32-FPXX-INV-NOT: sdc1 $f19,
; O32-FPXX-INV-NOT: sdc1 $f21,
; O32-FPXX-INV-NOT: sdc1 $f23,
; O32-FPXX-INV-NOT: sdc1 $f25,
; O32-FPXX-INV-NOT: sdc1 $f27,
; O32-FPXX-INV-NOT: sdc1 $f29,
; O32-FPXX-INV-NOT: sdc1 $f31,
; O32-FPXX: addiu $sp, $sp, -48
; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
; O32-FPXX-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)
; O32-FPXX-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
; O32-FPXX-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
; O32-FPXX-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
; O32-FPXX-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
; O32-FPXX-DAG: ldc1 [[F22]], [[OFF22]]($sp)
; O32-FPXX-DAG: ldc1 [[F24]], [[OFF24]]($sp)
; O32-FPXX-DAG: ldc1 [[F26]], [[OFF26]]($sp)
; O32-FPXX-DAG: ldc1 [[F28]], [[OFF28]]($sp)
; O32-FPXX-DAG: ldc1 [[F30]], [[OFF30]]($sp)
; O32-FPXX: addiu $sp, $sp, 48

24
test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
define void @fpu_clobber() nounwind {
entry:
call void asm "# Clobber", "~{$f21}"()
ret void
}
; O32-FPXX-LABEL: fpu_clobber:
; O32-FPXX: addiu $sp, $sp, -8
; O32-FP64-INV-NOT: sdc1 $f20,
; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
; O32-FPXX: addiu $sp, $sp, 8