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Reapply r97778 and r97779, enabled only for unsigned i64 to f64
conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97854 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2008,6 +2008,31 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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return Result;
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return Result;
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}
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}
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assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
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assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
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// Implementation of unsigned i64 to f64 following the algorithm in
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// __floatundidf in compiler_rt. This implementation has the advantage
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// of performing rounding correctly, both in the default rounding mode
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// and in all alternate rounding modes.
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// TODO: Generalize this for use with other types.
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if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
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SDValue TwoP52 =
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DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
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SDValue TwoP84PlusTwoP52 =
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DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
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SDValue TwoP84 =
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DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
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SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
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SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
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DAG.getConstant(32, MVT::i64));
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SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
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SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
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SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
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SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
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SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52);
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return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
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}
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SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
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SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
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SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
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SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
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