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[mips] Increase the number of floating point condition code registers to eight.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187234 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-07-26 19:03:48 +00:00
parent 9955cb931b
commit 0fc641df37
1 changed files with 5 additions and 3 deletions
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8
lib/Target/Mips/MipsRegisterInfo.td
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@ -181,8 +181,9 @@ let Namespace = "Mips" in {
foreach I = 0-31 in
def FCR#I : MipsReg<#I, ""#I>;
// fcc0 register
def FCC0 : MipsReg<0, "fcc0">;
// FP condition code registers.
foreach I = 0-7 in
def FCC#I : MipsReg<#I, "fcc"#I>;
// PC register
def PC : Register<"pc">;
@ -292,7 +293,8 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
Unallocatable;
// FP condition code registers.
def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable;
def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
Unallocatable;
// Hi/Lo Registers
def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;