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split machineoperand out into its own header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45445 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
6259d51c91
commit
103a64318b
@ -16,348 +16,16 @@
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/Support/DataTypes.h"
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#include <vector>
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#include <cassert>
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#include <iosfwd>
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#include "llvm/CodeGen/MachineOperand.h"
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namespace llvm {
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class Value;
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class Function;
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class MachineBasicBlock;
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class TargetInstrDescriptor;
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class TargetMachine;
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class GlobalValue;
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template <typename T> struct ilist_traits;
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template <typename T> struct ilist;
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//===----------------------------------------------------------------------===//
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// class MachineOperand
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//
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// Representation of each machine instruction operand.
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//
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struct MachineOperand {
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enum MachineOperandType {
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MO_Register, // Register operand.
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MO_Immediate, // Immediate Operand
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MO_MachineBasicBlock, // MachineBasicBlock reference
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MO_FrameIndex, // Abstract Stack Frame Index
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MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
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MO_JumpTableIndex, // Address of indexed Jump Table for switch
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MO_ExternalSymbol, // Name of external global symbol
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MO_GlobalAddress // Address of a global value
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};
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private:
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union {
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GlobalValue *GV; // For MO_GlobalAddress.
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
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const char *SymbolName; // For MO_ExternalSymbol.
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unsigned RegNo; // For MO_Register.
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int64_t immedVal; // For MO_Immediate and MO_*Index.
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} contents;
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MachineOperandType opType:8; // Discriminate the union.
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bool IsDef : 1; // True if this is a def, false if this is a use.
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bool IsImp : 1; // True if this is an implicit def or use.
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bool IsKill : 1; // True if this is a reg use and the reg is dead
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// immediately after the read.
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bool IsDead : 1; // True if this is a reg def and the reg is dead
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// immediately after the write. i.e. A register
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// that is defined but never used.
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/// auxInfo - auxiliary information used by the MachineOperand
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union {
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/// offset - Offset to address of global or external, only valid for
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/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
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int offset;
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/// subReg - SubRegister number, only valid for MO_Register. A value of 0
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/// indicates the MO_Register has no subReg.
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unsigned char subReg;
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} auxInfo;
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MachineOperand() {}
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void print(std::ostream &os) const;
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void print(std::ostream *os) const { if (os) print(*os); }
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public:
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MachineOperand(const MachineOperand &M) {
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*this = M;
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}
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~MachineOperand() {}
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/// getType - Returns the MachineOperandType for this operand.
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///
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MachineOperandType getType() const { return opType; }
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/// Accessors that tell you what kind of MachineOperand you're looking at.
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///
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bool isRegister() const { return opType == MO_Register; }
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bool isImmediate() const { return opType == MO_Immediate; }
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bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
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bool isFrameIndex() const { return opType == MO_FrameIndex; }
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bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
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bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; }
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bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
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bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
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int64_t getImm() const {
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assert(isImmediate() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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int64_t getImmedValue() const {
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assert(isImmediate() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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MachineBasicBlock *getMBB() const {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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MachineBasicBlock *getMachineBasicBlock() const {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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void setMachineBasicBlock(MachineBasicBlock *MBB) {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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contents.MBB = MBB;
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}
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int getFrameIndex() const {
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assert(isFrameIndex() && "Wrong MachineOperand accessor");
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return (int)contents.immedVal;
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}
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unsigned getConstantPoolIndex() const {
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assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
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return (unsigned)contents.immedVal;
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}
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unsigned getJumpTableIndex() const {
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assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
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return (unsigned)contents.immedVal;
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}
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GlobalValue *getGlobal() const {
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assert(isGlobalAddress() && "Wrong MachineOperand accessor");
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return contents.GV;
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}
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int getOffset() const {
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assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
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"Wrong MachineOperand accessor");
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return auxInfo.offset;
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}
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unsigned getSubReg() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return (unsigned)auxInfo.subReg;
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}
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const char *getSymbolName() const {
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assert(isExternalSymbol() && "Wrong MachineOperand accessor");
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return contents.SymbolName;
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}
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bool isUse() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return !IsDef;
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}
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bool isDef() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsDef;
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}
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void setIsUse() {
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assert(isRegister() && "Wrong MachineOperand accessor");
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IsDef = false;
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}
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void setIsDef() {
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assert(isRegister() && "Wrong MachineOperand accessor");
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IsDef = true;
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}
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bool isImplicit() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsImp;
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}
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void setImplicit() {
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assert(isRegister() && "Wrong MachineOperand accessor");
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IsImp = true;
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}
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bool isKill() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsKill;
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}
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bool isDead() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsDead;
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}
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void setIsKill() {
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assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
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IsKill = true;
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}
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void setIsDead() {
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assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
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IsDead = true;
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}
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void unsetIsKill() {
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assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
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IsKill = false;
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}
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void unsetIsDead() {
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assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
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IsDead = false;
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}
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/// getReg - Returns the register number.
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///
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unsigned getReg() const {
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assert(isRegister() && "This is not a register operand!");
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return contents.RegNo;
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}
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/// MachineOperand mutators.
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///
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void setReg(unsigned Reg) {
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assert(isRegister() && "This is not a register operand!");
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contents.RegNo = Reg;
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}
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void setImmedValue(int64_t immVal) {
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assert(isImmediate() && "Wrong MachineOperand mutator");
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contents.immedVal = immVal;
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}
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void setImm(int64_t immVal) {
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assert(isImmediate() && "Wrong MachineOperand mutator");
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contents.immedVal = immVal;
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}
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void setOffset(int Offset) {
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assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() ||
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isJumpTableIndex()) &&
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"Wrong MachineOperand accessor");
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auxInfo.offset = Offset;
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}
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void setSubReg(unsigned subReg) {
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assert(isRegister() && "Wrong MachineOperand accessor");
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auxInfo.subReg = (unsigned char)subReg;
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}
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void setConstantPoolIndex(unsigned Idx) {
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assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
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contents.immedVal = Idx;
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}
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void setJumpTableIndex(unsigned Idx) {
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assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
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contents.immedVal = Idx;
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}
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/// isIdenticalTo - Return true if this operand is identical to the specified
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/// operand. Note: This method ignores isKill and isDead properties.
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bool isIdenticalTo(const MachineOperand &Other) const;
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/// ChangeToImmediate - Replace this operand with a new immediate operand of
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/// the specified value. If an operand is known to be an immediate already,
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/// the setImmedValue method should be used.
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void ChangeToImmediate(int64_t ImmVal) {
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opType = MO_Immediate;
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contents.immedVal = ImmVal;
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}
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/// ChangeToRegister - Replace this operand with a new register operand of
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/// the specified value. If an operand is known to be an register already,
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/// the setReg method should be used.
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void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
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bool isKill = false, bool isDead = false) {
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opType = MO_Register;
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contents.RegNo = Reg;
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IsDef = isDef;
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IsImp = isImp;
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IsKill = isKill;
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IsDead = isDead;
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}
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static MachineOperand CreateImm(int64_t Val) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Immediate;
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Op.contents.immedVal = Val;
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Op.auxInfo.offset = 0;
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return Op;
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}
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static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
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bool isKill = false, bool isDead = false,
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unsigned SubReg = 0) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = isDef;
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Op.IsImp = isImp;
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Op.IsKill = isKill;
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Op.IsDead = isDead;
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Op.contents.RegNo = Reg;
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Op.auxInfo.subReg = SubReg;
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return Op;
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}
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static MachineOperand CreateMBB(MachineBasicBlock *MBB) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_MachineBasicBlock;
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Op.contents.MBB = MBB;
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Op.auxInfo.offset = 0;
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return Op;
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}
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static MachineOperand CreateFI(unsigned Idx) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_FrameIndex;
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Op.contents.immedVal = Idx;
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Op.auxInfo.offset = 0;
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return Op;
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}
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static MachineOperand CreateCPI(unsigned Idx, int Offset) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_ConstantPoolIndex;
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Op.contents.immedVal = Idx;
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Op.auxInfo.offset = Offset;
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return Op;
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}
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static MachineOperand CreateJTI(unsigned Idx) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_JumpTableIndex;
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Op.contents.immedVal = Idx;
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Op.auxInfo.offset = 0;
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return Op;
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}
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static MachineOperand CreateGA(GlobalValue *GV, int Offset) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_GlobalAddress;
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Op.contents.GV = GV;
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Op.auxInfo.offset = Offset;
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return Op;
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}
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static MachineOperand CreateES(const char *SymName, int Offset = 0) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_ExternalSymbol;
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Op.contents.SymbolName = SymName;
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Op.auxInfo.offset = Offset;
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return Op;
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}
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const MachineOperand &operator=(const MachineOperand &MO) {
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contents = MO.contents;
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IsDef = MO.IsDef;
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IsImp = MO.IsImp;
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IsKill = MO.IsKill;
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IsDead = MO.IsDead;
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opType = MO.opType;
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auxInfo = MO.auxInfo;
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return *this;
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}
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
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mop.print(os);
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return os;
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}
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friend class MachineInstr;
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};
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//===----------------------------------------------------------------------===//
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/// MachineInstr - Representation of each machine instruction.
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///
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@ -531,7 +199,6 @@ private:
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// Debugging Support
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std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
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std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
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} // End llvm namespace
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353
include/llvm/CodeGen/MachineOperand.h
Normal file
353
include/llvm/CodeGen/MachineOperand.h
Normal file
@ -0,0 +1,353 @@
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//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineOperand class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
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#define LLVM_CODEGEN_MACHINEOPERAND_H
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#include "llvm/Support/DataTypes.h"
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#include <vector>
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#include <cassert>
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#include <iosfwd>
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namespace llvm {
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class MachineBasicBlock;
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class GlobalValue;
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/// MachineOperand class - Representation of each machine instruction operand.
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///
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class MachineOperand {
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public:
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enum MachineOperandType {
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MO_Register, // Register operand.
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MO_Immediate, // Immediate Operand
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MO_MachineBasicBlock, // MachineBasicBlock reference
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MO_FrameIndex, // Abstract Stack Frame Index
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MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
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MO_JumpTableIndex, // Address of indexed Jump Table for switch
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MO_ExternalSymbol, // Name of external global symbol
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MO_GlobalAddress // Address of a global value
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};
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private:
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union {
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GlobalValue *GV; // For MO_GlobalAddress.
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
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const char *SymbolName; // For MO_ExternalSymbol.
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unsigned RegNo; // For MO_Register.
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int64_t immedVal; // For MO_Immediate and MO_*Index.
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} contents;
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MachineOperandType opType:8; // Discriminate the union.
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bool IsDef : 1; // True if this is a def, false if this is a use.
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bool IsImp : 1; // True if this is an implicit def or use.
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bool IsKill : 1; // True if this is a reg use and the reg is dead
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// immediately after the read.
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bool IsDead : 1; // True if this is a reg def and the reg is dead
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// immediately after the write. i.e. A register
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// that is defined but never used.
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/// auxInfo - auxiliary information used by the MachineOperand
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union {
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/// offset - Offset to address of global or external, only valid for
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/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
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int offset;
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/// subReg - SubRegister number, only valid for MO_Register. A value of 0
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/// indicates the MO_Register has no subReg.
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unsigned char subReg;
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} auxInfo;
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MachineOperand() {}
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void print(std::ostream &os) const;
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void print(std::ostream *os) const { if (os) print(*os); }
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public:
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MachineOperand(const MachineOperand &M) {
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*this = M;
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}
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~MachineOperand() {}
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/// getType - Returns the MachineOperandType for this operand.
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///
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MachineOperandType getType() const { return opType; }
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/// Accessors that tell you what kind of MachineOperand you're looking at.
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///
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bool isRegister() const { return opType == MO_Register; }
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bool isImmediate() const { return opType == MO_Immediate; }
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bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
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bool isFrameIndex() const { return opType == MO_FrameIndex; }
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bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
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bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; }
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bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
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bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
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int64_t getImm() const {
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assert(isImmediate() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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int64_t getImmedValue() const {
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assert(isImmediate() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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MachineBasicBlock *getMBB() const {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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MachineBasicBlock *getMachineBasicBlock() const {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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void setMachineBasicBlock(MachineBasicBlock *MBB) {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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contents.MBB = MBB;
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}
|
||||
int getFrameIndex() const {
|
||||
assert(isFrameIndex() && "Wrong MachineOperand accessor");
|
||||
return (int)contents.immedVal;
|
||||
}
|
||||
unsigned getConstantPoolIndex() const {
|
||||
assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
|
||||
return (unsigned)contents.immedVal;
|
||||
}
|
||||
unsigned getJumpTableIndex() const {
|
||||
assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
|
||||
return (unsigned)contents.immedVal;
|
||||
}
|
||||
GlobalValue *getGlobal() const {
|
||||
assert(isGlobalAddress() && "Wrong MachineOperand accessor");
|
||||
return contents.GV;
|
||||
}
|
||||
int getOffset() const {
|
||||
assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
|
||||
"Wrong MachineOperand accessor");
|
||||
return auxInfo.offset;
|
||||
}
|
||||
unsigned getSubReg() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return (unsigned)auxInfo.subReg;
|
||||
}
|
||||
const char *getSymbolName() const {
|
||||
assert(isExternalSymbol() && "Wrong MachineOperand accessor");
|
||||
return contents.SymbolName;
|
||||
}
|
||||
|
||||
bool isUse() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return !IsDef;
|
||||
}
|
||||
bool isDef() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsDef;
|
||||
}
|
||||
void setIsUse() {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsDef = false;
|
||||
}
|
||||
void setIsDef() {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsDef = true;
|
||||
}
|
||||
|
||||
bool isImplicit() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsImp;
|
||||
}
|
||||
void setImplicit() {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsImp = true;
|
||||
}
|
||||
|
||||
bool isKill() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsKill;
|
||||
}
|
||||
bool isDead() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsDead;
|
||||
}
|
||||
void setIsKill() {
|
||||
assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
|
||||
IsKill = true;
|
||||
}
|
||||
void setIsDead() {
|
||||
assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
|
||||
IsDead = true;
|
||||
}
|
||||
void unsetIsKill() {
|
||||
assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
|
||||
IsKill = false;
|
||||
}
|
||||
void unsetIsDead() {
|
||||
assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
|
||||
IsDead = false;
|
||||
}
|
||||
|
||||
/// getReg - Returns the register number.
|
||||
///
|
||||
unsigned getReg() const {
|
||||
assert(isRegister() && "This is not a register operand!");
|
||||
return contents.RegNo;
|
||||
}
|
||||
|
||||
/// MachineOperand mutators.
|
||||
///
|
||||
void setReg(unsigned Reg) {
|
||||
assert(isRegister() && "This is not a register operand!");
|
||||
contents.RegNo = Reg;
|
||||
}
|
||||
|
||||
void setImmedValue(int64_t immVal) {
|
||||
assert(isImmediate() && "Wrong MachineOperand mutator");
|
||||
contents.immedVal = immVal;
|
||||
}
|
||||
void setImm(int64_t immVal) {
|
||||
assert(isImmediate() && "Wrong MachineOperand mutator");
|
||||
contents.immedVal = immVal;
|
||||
}
|
||||
|
||||
void setOffset(int Offset) {
|
||||
assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() ||
|
||||
isJumpTableIndex()) &&
|
||||
"Wrong MachineOperand accessor");
|
||||
auxInfo.offset = Offset;
|
||||
}
|
||||
void setSubReg(unsigned subReg) {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
auxInfo.subReg = (unsigned char)subReg;
|
||||
}
|
||||
void setConstantPoolIndex(unsigned Idx) {
|
||||
assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
|
||||
contents.immedVal = Idx;
|
||||
}
|
||||
void setJumpTableIndex(unsigned Idx) {
|
||||
assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
|
||||
contents.immedVal = Idx;
|
||||
}
|
||||
|
||||
/// isIdenticalTo - Return true if this operand is identical to the specified
|
||||
/// operand. Note: This method ignores isKill and isDead properties.
|
||||
bool isIdenticalTo(const MachineOperand &Other) const;
|
||||
|
||||
/// ChangeToImmediate - Replace this operand with a new immediate operand of
|
||||
/// the specified value. If an operand is known to be an immediate already,
|
||||
/// the setImmedValue method should be used.
|
||||
void ChangeToImmediate(int64_t ImmVal) {
|
||||
opType = MO_Immediate;
|
||||
contents.immedVal = ImmVal;
|
||||
}
|
||||
|
||||
/// ChangeToRegister - Replace this operand with a new register operand of
|
||||
/// the specified value. If an operand is known to be an register already,
|
||||
/// the setReg method should be used.
|
||||
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
|
||||
bool isKill = false, bool isDead = false) {
|
||||
opType = MO_Register;
|
||||
contents.RegNo = Reg;
|
||||
IsDef = isDef;
|
||||
IsImp = isImp;
|
||||
IsKill = isKill;
|
||||
IsDead = isDead;
|
||||
}
|
||||
|
||||
static MachineOperand CreateImm(int64_t Val) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_Immediate;
|
||||
Op.contents.immedVal = Val;
|
||||
Op.auxInfo.offset = 0;
|
||||
return Op;
|
||||
}
|
||||
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
|
||||
bool isKill = false, bool isDead = false,
|
||||
unsigned SubReg = 0) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_Register;
|
||||
Op.IsDef = isDef;
|
||||
Op.IsImp = isImp;
|
||||
Op.IsKill = isKill;
|
||||
Op.IsDead = isDead;
|
||||
Op.contents.RegNo = Reg;
|
||||
Op.auxInfo.subReg = SubReg;
|
||||
return Op;
|
||||
}
|
||||
static MachineOperand CreateMBB(MachineBasicBlock *MBB) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_MachineBasicBlock;
|
||||
Op.contents.MBB = MBB;
|
||||
Op.auxInfo.offset = 0;
|
||||
return Op;
|
||||
}
|
||||
static MachineOperand CreateFI(unsigned Idx) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_FrameIndex;
|
||||
Op.contents.immedVal = Idx;
|
||||
Op.auxInfo.offset = 0;
|
||||
return Op;
|
||||
}
|
||||
static MachineOperand CreateCPI(unsigned Idx, int Offset) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_ConstantPoolIndex;
|
||||
Op.contents.immedVal = Idx;
|
||||
Op.auxInfo.offset = Offset;
|
||||
return Op;
|
||||
}
|
||||
static MachineOperand CreateJTI(unsigned Idx) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_JumpTableIndex;
|
||||
Op.contents.immedVal = Idx;
|
||||
Op.auxInfo.offset = 0;
|
||||
return Op;
|
||||
}
|
||||
static MachineOperand CreateGA(GlobalValue *GV, int Offset) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_GlobalAddress;
|
||||
Op.contents.GV = GV;
|
||||
Op.auxInfo.offset = Offset;
|
||||
return Op;
|
||||
}
|
||||
static MachineOperand CreateES(const char *SymName, int Offset = 0) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_ExternalSymbol;
|
||||
Op.contents.SymbolName = SymName;
|
||||
Op.auxInfo.offset = Offset;
|
||||
return Op;
|
||||
}
|
||||
const MachineOperand &operator=(const MachineOperand &MO) {
|
||||
contents = MO.contents;
|
||||
IsDef = MO.IsDef;
|
||||
IsImp = MO.IsImp;
|
||||
IsKill = MO.IsKill;
|
||||
IsDead = MO.IsDead;
|
||||
opType = MO.opType;
|
||||
auxInfo = MO.auxInfo;
|
||||
return *this;
|
||||
}
|
||||
|
||||
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
|
||||
mop.print(os);
|
||||
return os;
|
||||
}
|
||||
|
||||
friend class MachineInstr;
|
||||
};
|
||||
|
||||
std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user