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ARM::tPOP and tPOP_RET each has an extra writeback operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1359,9 +1359,11 @@ bool ARMConstantIslands::UndoLRSpillRestore() {
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bool MadeChange = false;
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for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
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MachineInstr *MI = PushPopMIs[i];
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// First two operands are predicates, the third is a zero since there
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// is no writeback.
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if (MI->getOpcode() == ARM::tPOP_RET &&
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MI->getOperand(2).getReg() == ARM::PC &&
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MI->getNumExplicitOperands() == 3) {
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MI->getOperand(3).getReg() == ARM::PC &&
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MI->getNumExplicitOperands() == 4) {
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BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
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MI->eraseFromParent();
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MadeChange = true;
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@ -178,6 +178,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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DebugLoc DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
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AddDefaultPred(MIB);
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MIB.addReg(0); // No write back.
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bool NumRegs = 0;
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for (unsigned i = CSI.size(); i != 0; --i) {
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@ -863,6 +863,7 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
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// Epilogue for vararg functions: pop LR to R3 and branch off it.
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// FIXME: Verify this is still ok when R3 is no longer being reserved.
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
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.addReg(0) // No write back.
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.addReg(ARM::R3, RegState::Define);
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emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
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13
test/CodeGen/Thumb/pop.ll
Normal file
13
test/CodeGen/Thumb/pop.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
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; rdar://7268481
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define arm_apcscc void @t(i8* %a, ...) nounwind {
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; CHECK: t:
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; CHECK: pop {r3}
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; CHECK-NEXT: add sp, #3 * 4
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; CHECK-NEXT: bx r3
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entry:
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%a.addr = alloca i8*
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store i8* %a, i8** %a.addr
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ret void
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}
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