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Remove a bogus optimization. It's not possible to do a move to low element to a <8 x i16> or <16 x i8> vector.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44669 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-12-06 22:14:22 +00:00
parent b0e370abdf
commit 1076210ee3
2 changed files with 1 additions and 7 deletions
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2
lib/Target/X86/X86ISelLowering.cpp
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@ -2462,7 +2462,7 @@ bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
/// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element.
static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
if (NumElts != 2 && NumElts != 4)
return false;
if (!isUndefOrEqual(Elts[0], NumElts))

6
lib/Target/X86/X86InstrSSE.td
View File

@ -2734,12 +2734,6 @@ let Predicates = [HasSSE2] in {
// Move scalar to XMM zero-extended
// movd to XMM register zero-extends
let AddedComplexity = 15 in {
def : Pat<(v8i16 (vector_shuffle immAllZerosV_bc,
(v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
(MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
def : Pat<(v16i8 (vector_shuffle immAllZerosV_bc,
(v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
(MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
(v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),