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https://github.com/RPCS3/llvm.git
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[NVPTX] Implement fma and imad contraction as target DAGCombiner patterns
This also introduces DAGCombiner patterns for mul.wide to multiply two smaller integers and produce a larger integer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211935 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
508c80f11f
commit
10da1651ed
@ -24,11 +24,14 @@ using namespace llvm;
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#define DEBUG_TYPE "nvptx-isel"
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static cl::opt<int>
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FMAContractLevel("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
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cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
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" 1: do it 2: do it aggressively"),
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cl::init(2));
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unsigned FMAContractLevel = 0;
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static cl::opt<unsigned, true>
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FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
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cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
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" 1: do it 2: do it aggressively"),
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cl::location(FMAContractLevel),
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cl::init(2));
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static cl::opt<int> UsePrecDivF32(
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"nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
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@ -243,6 +243,13 @@ NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
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setOperationAction(ISD::CTPOP, MVT::i32, Legal);
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setOperationAction(ISD::CTPOP, MVT::i64, Legal);
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// We have some custom DAG combine patterns for these nodes
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::MUL);
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setTargetDAGCombine(ISD::SHL);
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// Now deduce the information based on the above mentioned
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// actions
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computeRegisterProperties();
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@ -334,6 +341,10 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "NVPTXISD::StoreV2";
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case NVPTXISD::StoreV4:
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return "NVPTXISD::StoreV4";
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case NVPTXISD::FUN_SHFL_CLAMP:
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return "NVPTXISD::FUN_SHFL_CLAMP";
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case NVPTXISD::FUN_SHFR_CLAMP:
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return "NVPTXISD::FUN_SHFR_CLAMP";
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case NVPTXISD::Tex1DFloatI32: return "NVPTXISD::Tex1DFloatI32";
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case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
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case NVPTXISD::Tex1DFloatFloatLevel:
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@ -2475,6 +2486,406 @@ unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
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return 4;
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}
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//===----------------------------------------------------------------------===//
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// NVPTX DAG Combining
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//===----------------------------------------------------------------------===//
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extern unsigned FMAContractLevel;
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/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
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/// operands N0 and N1. This is a helper for PerformADDCombine that is
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/// called with the default operands, and if that fails, with commuted
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/// operands.
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static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
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TargetLowering::DAGCombinerInfo &DCI,
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const NVPTXSubtarget &Subtarget,
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CodeGenOpt::Level OptLevel) {
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SelectionDAG &DAG = DCI.DAG;
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// Skip non-integer, non-scalar case
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EVT VT=N0.getValueType();
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if (VT.isVector())
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return SDValue();
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// fold (add (mul a, b), c) -> (mad a, b, c)
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//
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if (N0.getOpcode() == ISD::MUL) {
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assert (VT.isInteger());
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// For integer:
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// Since integer multiply-add costs the same as integer multiply
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// but is more costly than integer add, do the fusion only when
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// the mul is only used in the add.
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if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
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!N0.getNode()->hasOneUse())
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return SDValue();
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// Do the folding
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return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
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N0.getOperand(0), N0.getOperand(1), N1);
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}
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else if (N0.getOpcode() == ISD::FMUL) {
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if (VT == MVT::f32 || VT == MVT::f64) {
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if (FMAContractLevel == 0)
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return SDValue();
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// For floating point:
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// Do the fusion only when the mul has less than 5 uses and all
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// are add.
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// The heuristic is that if a use is not an add, then that use
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// cannot be fused into fma, therefore mul is still needed anyway.
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// If there are more than 4 uses, even if they are all add, fusing
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// them will increase register pressue.
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//
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int numUses = 0;
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int nonAddCount = 0;
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for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
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UE = N0.getNode()->use_end();
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UI != UE; ++UI) {
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numUses++;
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SDNode *User = *UI;
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if (User->getOpcode() != ISD::FADD)
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++nonAddCount;
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}
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if (numUses >= 5)
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return SDValue();
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if (nonAddCount) {
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int orderNo = N->getIROrder();
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int orderNo2 = N0.getNode()->getIROrder();
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// simple heuristics here for considering potential register
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// pressure, the logics here is that the differnce are used
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// to measure the distance between def and use, the longer distance
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// more likely cause register pressure.
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if (orderNo - orderNo2 < 500)
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return SDValue();
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// Now, check if at least one of the FMUL's operands is live beyond the node N,
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// which guarantees that the FMA will not increase register pressure at node N.
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bool opIsLive = false;
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const SDNode *left = N0.getOperand(0).getNode();
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const SDNode *right = N0.getOperand(1).getNode();
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if (dyn_cast<ConstantSDNode>(left) || dyn_cast<ConstantSDNode>(right))
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opIsLive = true;
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if (!opIsLive)
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for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
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SDNode *User = *UI;
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int orderNo3 = User->getIROrder();
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if (orderNo3 > orderNo) {
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opIsLive = true;
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break;
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}
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}
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if (!opIsLive)
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for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
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SDNode *User = *UI;
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int orderNo3 = User->getIROrder();
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if (orderNo3 > orderNo) {
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opIsLive = true;
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break;
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}
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}
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if (!opIsLive)
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return SDValue();
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}
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return DAG.getNode(ISD::FMA, SDLoc(N), VT,
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N0.getOperand(0), N0.getOperand(1), N1);
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}
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}
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return SDValue();
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}
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/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
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///
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static SDValue PerformADDCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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const NVPTXSubtarget &Subtarget,
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CodeGenOpt::Level OptLevel) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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// First try with the default operand order.
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SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
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OptLevel);
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if (Result.getNode())
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return Result;
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// If that didn't work, try again with the operands commuted.
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return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
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}
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static SDValue PerformANDCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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// The type legalizer turns a vector load of i8 values into a zextload to i16
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// registers, optionally ANY_EXTENDs it (if target type is integer),
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// and ANDs off the high 8 bits. Since we turn this load into a
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// target-specific DAG node, the DAG combiner fails to eliminate these AND
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// nodes. Do that here.
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SDValue Val = N->getOperand(0);
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SDValue Mask = N->getOperand(1);
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if (isa<ConstantSDNode>(Val)) {
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std::swap(Val, Mask);
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}
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SDValue AExt;
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// Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
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if (Val.getOpcode() == ISD::ANY_EXTEND) {
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AExt = Val;
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Val = Val->getOperand(0);
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}
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if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
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Val = Val->getOperand(0);
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}
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if (Val->getOpcode() == NVPTXISD::LoadV2 ||
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Val->getOpcode() == NVPTXISD::LoadV4) {
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ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
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if (!MaskCnst) {
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// Not an AND with a constant
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return SDValue();
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}
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uint64_t MaskVal = MaskCnst->getZExtValue();
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if (MaskVal != 0xff) {
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// Not an AND that chops off top 8 bits
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return SDValue();
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}
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MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
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if (!Mem) {
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// Not a MemSDNode?!?
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return SDValue();
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}
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EVT MemVT = Mem->getMemoryVT();
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if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
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// We only handle the i8 case
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return SDValue();
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}
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unsigned ExtType =
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cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
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getZExtValue();
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if (ExtType == ISD::SEXTLOAD) {
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// If for some reason the load is a sextload, the and is needed to zero
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// out the high 8 bits
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return SDValue();
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}
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bool AddTo = false;
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if (AExt.getNode() != 0) {
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// Re-insert the ext as a zext.
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Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
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AExt.getValueType(), Val);
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AddTo = true;
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}
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// If we get here, the AND is unnecessary. Just replace it with the load
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DCI.CombineTo(N, Val, AddTo);
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}
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return SDValue();
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}
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enum OperandSignedness {
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Signed = 0,
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Unsigned,
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Unknown
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};
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/// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
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/// that can be demoted to \p OptSize bits without loss of information. The
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/// signedness of the operand, if determinable, is placed in \p S.
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static bool IsMulWideOperandDemotable(SDValue Op,
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unsigned OptSize,
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OperandSignedness &S) {
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S = Unknown;
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if (Op.getOpcode() == ISD::SIGN_EXTEND ||
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Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
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EVT OrigVT = Op.getOperand(0).getValueType();
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if (OrigVT.getSizeInBits() == OptSize) {
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S = Signed;
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return true;
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}
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} else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
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EVT OrigVT = Op.getOperand(0).getValueType();
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if (OrigVT.getSizeInBits() == OptSize) {
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S = Unsigned;
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return true;
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}
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}
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return false;
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}
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/// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
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/// be demoted to \p OptSize bits without loss of information. If the operands
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/// contain a constant, it should appear as the RHS operand. The signedness of
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/// the operands is placed in \p IsSigned.
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static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
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unsigned OptSize,
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bool &IsSigned) {
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OperandSignedness LHSSign;
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// The LHS operand must be a demotable op
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if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
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return false;
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// We should have been able to determine the signedness from the LHS
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if (LHSSign == Unknown)
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return false;
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IsSigned = (LHSSign == Signed);
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// The RHS can be a demotable op or a constant
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if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
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APInt Val = CI->getAPIntValue();
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if (LHSSign == Unsigned) {
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if (Val.isIntN(OptSize)) {
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return true;
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}
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return false;
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} else {
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if (Val.isSignedIntN(OptSize)) {
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return true;
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}
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return false;
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}
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} else {
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OperandSignedness RHSSign;
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if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
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return false;
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if (LHSSign != RHSSign)
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return false;
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return true;
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}
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}
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/// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
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/// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
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/// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
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/// amount.
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static SDValue TryMULWIDECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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EVT MulType = N->getValueType(0);
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if (MulType != MVT::i32 && MulType != MVT::i64) {
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return SDValue();
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}
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unsigned OptSize = MulType.getSizeInBits() >> 1;
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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// Canonicalize the multiply so the constant (if any) is on the right
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if (N->getOpcode() == ISD::MUL) {
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if (isa<ConstantSDNode>(LHS)) {
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std::swap(LHS, RHS);
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}
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}
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// If we have a SHL, determine the actual multiply amount
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if (N->getOpcode() == ISD::SHL) {
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ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
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if (!ShlRHS) {
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return SDValue();
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}
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APInt ShiftAmt = ShlRHS->getAPIntValue();
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unsigned BitWidth = MulType.getSizeInBits();
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if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
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APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
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RHS = DCI.DAG.getConstant(MulVal, MulType);
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} else {
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return SDValue();
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}
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}
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bool Signed;
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// Verify that our operands are demotable
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if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
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return SDValue();
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}
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EVT DemotedVT;
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if (MulType == MVT::i32) {
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DemotedVT = MVT::i16;
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} else {
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DemotedVT = MVT::i32;
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}
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// Truncate the operands to the correct size. Note that these are just for
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// type consistency and will (likely) be eliminated in later phases.
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SDValue TruncLHS =
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DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
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SDValue TruncRHS =
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DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
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unsigned Opc;
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if (Signed) {
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Opc = NVPTXISD::MUL_WIDE_SIGNED;
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} else {
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Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
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}
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return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
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}
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/// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
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static SDValue PerformMULCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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CodeGenOpt::Level OptLevel) {
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if (OptLevel > 0) {
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// Try mul.wide combining at OptLevel > 0
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SDValue Ret = TryMULWIDECombine(N, DCI);
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if (Ret.getNode())
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return Ret;
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}
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return SDValue();
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}
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/// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
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static SDValue PerformSHLCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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CodeGenOpt::Level OptLevel) {
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if (OptLevel > 0) {
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// Try mul.wide combining at OptLevel > 0
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SDValue Ret = TryMULWIDECombine(N, DCI);
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if (Ret.getNode())
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return Ret;
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}
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return SDValue();
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}
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SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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// FIXME: Get this from the DAG somehow
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CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
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switch (N->getOpcode()) {
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default: break;
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case ISD::ADD:
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case ISD::FADD:
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return PerformADDCombine(N, DCI, nvptxSubtarget, OptLevel);
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case ISD::MUL:
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return PerformMULCombine(N, DCI, OptLevel);
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case ISD::SHL:
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return PerformSHLCombine(N, DCI, OptLevel);
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case ISD::AND:
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return PerformANDCombine(N, DCI);
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}
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||||
return SDValue();
|
||||
}
|
||||
|
||||
/// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
|
||||
static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
|
||||
@ -49,6 +49,9 @@ enum NodeType {
|
||||
CallSeqBegin,
|
||||
CallSeqEnd,
|
||||
CallPrototype,
|
||||
MUL_WIDE_SIGNED,
|
||||
MUL_WIDE_UNSIGNED,
|
||||
IMAD,
|
||||
Dummy,
|
||||
|
||||
LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
||||
@ -258,6 +261,7 @@ private:
|
||||
|
||||
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
|
||||
SelectionDAG &DAG) const override;
|
||||
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
||||
|
||||
unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
|
||||
Type *Ty, unsigned Idx) const;
|
||||
|
||||
@ -464,33 +464,45 @@ def SHL2MUL16 : SDNodeXForm<imm, [{
|
||||
return CurDAG->getTargetConstant(temp.shl(v), MVT::i16);
|
||||
}]>;
|
||||
|
||||
def MULWIDES64 : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int32Regs:$a, Int32Regs:$b),
|
||||
def MULWIDES64
|
||||
: NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
|
||||
"mul.wide.s32 \t$dst, $a, $b;", []>;
|
||||
def MULWIDES64Imm
|
||||
: NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
|
||||
"mul.wide.s32 \t$dst, $a, $b;", []>;
|
||||
def MULWIDES64Imm : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int32Regs:$a, i64imm:$b),
|
||||
def MULWIDES64Imm64
|
||||
: NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i64imm:$b),
|
||||
"mul.wide.s32 \t$dst, $a, $b;", []>;
|
||||
|
||||
def MULWIDEU64 : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int32Regs:$a, Int32Regs:$b),
|
||||
def MULWIDEU64
|
||||
: NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
|
||||
"mul.wide.u32 \t$dst, $a, $b;", []>;
|
||||
def MULWIDEU64Imm
|
||||
: NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
|
||||
"mul.wide.u32 \t$dst, $a, $b;", []>;
|
||||
def MULWIDEU64Imm : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int32Regs:$a, i64imm:$b),
|
||||
def MULWIDEU64Imm64
|
||||
: NVPTXInst<(outs Int64Regs:$dst), (ins Int32Regs:$a, i64imm:$b),
|
||||
"mul.wide.u32 \t$dst, $a, $b;", []>;
|
||||
|
||||
def MULWIDES32 : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int16Regs:$a, Int16Regs:$b),
|
||||
def MULWIDES32
|
||||
: NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
|
||||
"mul.wide.s16 \t$dst, $a, $b;", []>;
|
||||
def MULWIDES32Imm : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int16Regs:$a, i32imm:$b),
|
||||
def MULWIDES32Imm
|
||||
: NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
|
||||
"mul.wide.s16 \t$dst, $a, $b;", []>;
|
||||
def MULWIDES32Imm32
|
||||
: NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
|
||||
"mul.wide.s16 \t$dst, $a, $b;", []>;
|
||||
|
||||
def MULWIDEU32 : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int16Regs:$a, Int16Regs:$b),
|
||||
"mul.wide.u16 \t$dst, $a, $b;", []>;
|
||||
def MULWIDEU32Imm : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int16Regs:$a, i32imm:$b),
|
||||
def MULWIDEU32
|
||||
: NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
|
||||
"mul.wide.u16 \t$dst, $a, $b;", []>;
|
||||
def MULWIDEU32Imm
|
||||
: NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
|
||||
"mul.wide.u16 \t$dst, $a, $b;", []>;
|
||||
def MULWIDEU32Imm32
|
||||
: NVPTXInst<(outs Int32Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
|
||||
"mul.wide.u16 \t$dst, $a, $b;", []>;
|
||||
|
||||
def : Pat<(shl (sext Int32Regs:$a), (i32 Int5Const:$b)),
|
||||
(MULWIDES64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
|
||||
@ -510,25 +522,63 @@ def : Pat<(mul (sext Int32Regs:$a), (sext Int32Regs:$b)),
|
||||
(MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(mul (sext Int32Regs:$a), (i64 SInt32Const:$b)),
|
||||
(MULWIDES64Imm Int32Regs:$a, (i64 SInt32Const:$b))>,
|
||||
(MULWIDES64Imm64 Int32Regs:$a, (i64 SInt32Const:$b))>,
|
||||
Requires<[doMulWide]>;
|
||||
|
||||
def : Pat<(mul (zext Int32Regs:$a), (zext Int32Regs:$b)),
|
||||
(MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>, Requires<[doMulWide]>;
|
||||
(MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(mul (zext Int32Regs:$a), (i64 UInt32Const:$b)),
|
||||
(MULWIDEU64Imm Int32Regs:$a, (i64 UInt32Const:$b))>,
|
||||
(MULWIDEU64Imm64 Int32Regs:$a, (i64 UInt32Const:$b))>,
|
||||
Requires<[doMulWide]>;
|
||||
|
||||
def : Pat<(mul (sext Int16Regs:$a), (sext Int16Regs:$b)),
|
||||
(MULWIDES32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
|
||||
(MULWIDES32 Int16Regs:$a, Int16Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(mul (sext Int16Regs:$a), (i32 SInt16Const:$b)),
|
||||
(MULWIDES32Imm Int16Regs:$a, (i32 SInt16Const:$b))>,
|
||||
(MULWIDES32Imm32 Int16Regs:$a, (i32 SInt16Const:$b))>,
|
||||
Requires<[doMulWide]>;
|
||||
|
||||
def : Pat<(mul (zext Int16Regs:$a), (zext Int16Regs:$b)),
|
||||
(MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
|
||||
(MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(mul (zext Int16Regs:$a), (i32 UInt16Const:$b)),
|
||||
(MULWIDEU32Imm Int16Regs:$a, (i32 UInt16Const:$b))>,
|
||||
(MULWIDEU32Imm32 Int16Regs:$a, (i32 UInt16Const:$b))>,
|
||||
Requires<[doMulWide]>;
|
||||
|
||||
|
||||
def SDTMulWide
|
||||
: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>]>;
|
||||
def mul_wide_signed
|
||||
: SDNode<"NVPTXISD::MUL_WIDE_SIGNED", SDTMulWide>;
|
||||
def mul_wide_unsigned
|
||||
: SDNode<"NVPTXISD::MUL_WIDE_UNSIGNED", SDTMulWide>;
|
||||
|
||||
def : Pat<(i32 (mul_wide_signed Int16Regs:$a, Int16Regs:$b)),
|
||||
(MULWIDES32 Int16Regs:$a, Int16Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(i32 (mul_wide_signed Int16Regs:$a, imm:$b)),
|
||||
(MULWIDES32Imm Int16Regs:$a, imm:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(i32 (mul_wide_unsigned Int16Regs:$a, Int16Regs:$b)),
|
||||
(MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(i32 (mul_wide_unsigned Int16Regs:$a, imm:$b)),
|
||||
(MULWIDEU32Imm Int16Regs:$a, imm:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
|
||||
|
||||
def : Pat<(i64 (mul_wide_signed Int32Regs:$a, Int32Regs:$b)),
|
||||
(MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(i64 (mul_wide_signed Int32Regs:$a, imm:$b)),
|
||||
(MULWIDES64Imm Int32Regs:$a, imm:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(i64 (mul_wide_unsigned Int32Regs:$a, Int32Regs:$b)),
|
||||
(MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
def : Pat<(i64 (mul_wide_unsigned Int32Regs:$a, imm:$b)),
|
||||
(MULWIDEU64Imm Int32Regs:$a, imm:$b)>,
|
||||
Requires<[doMulWide]>;
|
||||
|
||||
defm MULT : I3<"mul.lo.s", mul>;
|
||||
@ -544,69 +594,75 @@ defm SREM : I3<"rem.s", srem>;
|
||||
defm UREM : I3<"rem.u", urem>;
|
||||
// The ri version will not be selected as DAGCombiner::visitUREM will lower it.
|
||||
|
||||
def SDTIMAD
|
||||
: SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>,
|
||||
SDTCisInt<2>, SDTCisSameAs<0, 2>,
|
||||
SDTCisSameAs<0, 3>]>;
|
||||
def imad
|
||||
: SDNode<"NVPTXISD::IMAD", SDTIMAD>;
|
||||
|
||||
def MAD16rrr : NVPTXInst<(outs Int16Regs:$dst),
|
||||
(ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
|
||||
"mad.lo.s16 \t$dst, $a, $b, $c;",
|
||||
[(set Int16Regs:$dst, (add
|
||||
(mul Int16Regs:$a, Int16Regs:$b), Int16Regs:$c))]>;
|
||||
[(set Int16Regs:$dst,
|
||||
(imad Int16Regs:$a, Int16Regs:$b, Int16Regs:$c))]>;
|
||||
def MAD16rri : NVPTXInst<(outs Int16Regs:$dst),
|
||||
(ins Int16Regs:$a, Int16Regs:$b, i16imm:$c),
|
||||
"mad.lo.s16 \t$dst, $a, $b, $c;",
|
||||
[(set Int16Regs:$dst, (add
|
||||
(mul Int16Regs:$a, Int16Regs:$b), imm:$c))]>;
|
||||
[(set Int16Regs:$dst,
|
||||
(imad Int16Regs:$a, Int16Regs:$b, imm:$c))]>;
|
||||
def MAD16rir : NVPTXInst<(outs Int16Regs:$dst),
|
||||
(ins Int16Regs:$a, i16imm:$b, Int16Regs:$c),
|
||||
"mad.lo.s16 \t$dst, $a, $b, $c;",
|
||||
[(set Int16Regs:$dst, (add
|
||||
(mul Int16Regs:$a, imm:$b), Int16Regs:$c))]>;
|
||||
[(set Int16Regs:$dst,
|
||||
(imad Int16Regs:$a, imm:$b, Int16Regs:$c))]>;
|
||||
def MAD16rii : NVPTXInst<(outs Int16Regs:$dst),
|
||||
(ins Int16Regs:$a, i16imm:$b, i16imm:$c),
|
||||
"mad.lo.s16 \t$dst, $a, $b, $c;",
|
||||
[(set Int16Regs:$dst, (add (mul Int16Regs:$a, imm:$b),
|
||||
imm:$c))]>;
|
||||
[(set Int16Regs:$dst,
|
||||
(imad Int16Regs:$a, imm:$b, imm:$c))]>;
|
||||
|
||||
def MAD32rrr : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
|
||||
"mad.lo.s32 \t$dst, $a, $b, $c;",
|
||||
[(set Int32Regs:$dst, (add
|
||||
(mul Int32Regs:$a, Int32Regs:$b), Int32Regs:$c))]>;
|
||||
[(set Int32Regs:$dst,
|
||||
(imad Int32Regs:$a, Int32Regs:$b, Int32Regs:$c))]>;
|
||||
def MAD32rri : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int32Regs:$a, Int32Regs:$b, i32imm:$c),
|
||||
"mad.lo.s32 \t$dst, $a, $b, $c;",
|
||||
[(set Int32Regs:$dst, (add
|
||||
(mul Int32Regs:$a, Int32Regs:$b), imm:$c))]>;
|
||||
[(set Int32Regs:$dst,
|
||||
(imad Int32Regs:$a, Int32Regs:$b, imm:$c))]>;
|
||||
def MAD32rir : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int32Regs:$a, i32imm:$b, Int32Regs:$c),
|
||||
"mad.lo.s32 \t$dst, $a, $b, $c;",
|
||||
[(set Int32Regs:$dst, (add
|
||||
(mul Int32Regs:$a, imm:$b), Int32Regs:$c))]>;
|
||||
[(set Int32Regs:$dst,
|
||||
(imad Int32Regs:$a, imm:$b, Int32Regs:$c))]>;
|
||||
def MAD32rii : NVPTXInst<(outs Int32Regs:$dst),
|
||||
(ins Int32Regs:$a, i32imm:$b, i32imm:$c),
|
||||
"mad.lo.s32 \t$dst, $a, $b, $c;",
|
||||
[(set Int32Regs:$dst, (add
|
||||
(mul Int32Regs:$a, imm:$b), imm:$c))]>;
|
||||
[(set Int32Regs:$dst,
|
||||
(imad Int32Regs:$a, imm:$b, imm:$c))]>;
|
||||
|
||||
def MAD64rrr : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int64Regs:$a, Int64Regs:$b, Int64Regs:$c),
|
||||
"mad.lo.s64 \t$dst, $a, $b, $c;",
|
||||
[(set Int64Regs:$dst, (add
|
||||
(mul Int64Regs:$a, Int64Regs:$b), Int64Regs:$c))]>;
|
||||
[(set Int64Regs:$dst,
|
||||
(imad Int64Regs:$a, Int64Regs:$b, Int64Regs:$c))]>;
|
||||
def MAD64rri : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int64Regs:$a, Int64Regs:$b, i64imm:$c),
|
||||
"mad.lo.s64 \t$dst, $a, $b, $c;",
|
||||
[(set Int64Regs:$dst, (add
|
||||
(mul Int64Regs:$a, Int64Regs:$b), imm:$c))]>;
|
||||
[(set Int64Regs:$dst,
|
||||
(imad Int64Regs:$a, Int64Regs:$b, imm:$c))]>;
|
||||
def MAD64rir : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int64Regs:$a, i64imm:$b, Int64Regs:$c),
|
||||
"mad.lo.s64 \t$dst, $a, $b, $c;",
|
||||
[(set Int64Regs:$dst, (add
|
||||
(mul Int64Regs:$a, imm:$b), Int64Regs:$c))]>;
|
||||
[(set Int64Regs:$dst,
|
||||
(imad Int64Regs:$a, imm:$b, Int64Regs:$c))]>;
|
||||
def MAD64rii : NVPTXInst<(outs Int64Regs:$dst),
|
||||
(ins Int64Regs:$a, i64imm:$b, i64imm:$c),
|
||||
"mad.lo.s64 \t$dst, $a, $b, $c;",
|
||||
[(set Int64Regs:$dst, (add
|
||||
(mul Int64Regs:$a, imm:$b), imm:$c))]>;
|
||||
|
||||
[(set Int64Regs:$dst,
|
||||
(imad Int64Regs:$a, imm:$b, imm:$c))]>;
|
||||
|
||||
def INEG16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
|
||||
"neg.s16 \t$dst, $src;",
|
||||
@ -812,36 +868,26 @@ multiclass FPCONTRACT32<string OpcStr, Predicate Pred> {
|
||||
def rrr : NVPTXInst<(outs Float32Regs:$dst),
|
||||
(ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float32Regs:$dst, (fadd
|
||||
(fmul Float32Regs:$a, Float32Regs:$b),
|
||||
Float32Regs:$c))]>, Requires<[Pred]>;
|
||||
// This is to WAR a weird bug in Tablegen that does not automatically
|
||||
// generate the following permutated rule rrr2 from the above rrr.
|
||||
// So we explicitly add it here. This happens to FMA32 only.
|
||||
// See the comments at FMAD32 and FMA32 for more information.
|
||||
def rrr2 : NVPTXInst<(outs Float32Regs:$dst),
|
||||
(ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float32Regs:$dst, (fadd Float32Regs:$c,
|
||||
(fmul Float32Regs:$a, Float32Regs:$b)))]>,
|
||||
[(set Float32Regs:$dst,
|
||||
(fma Float32Regs:$a, Float32Regs:$b, Float32Regs:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
def rri : NVPTXInst<(outs Float32Regs:$dst),
|
||||
(ins Float32Regs:$a, Float32Regs:$b, f32imm:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float32Regs:$dst, (fadd
|
||||
(fmul Float32Regs:$a, Float32Regs:$b), fpimm:$c))]>,
|
||||
[(set Float32Regs:$dst,
|
||||
(fma Float32Regs:$a, Float32Regs:$b, fpimm:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
def rir : NVPTXInst<(outs Float32Regs:$dst),
|
||||
(ins Float32Regs:$a, f32imm:$b, Float32Regs:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float32Regs:$dst, (fadd
|
||||
(fmul Float32Regs:$a, fpimm:$b), Float32Regs:$c))]>,
|
||||
[(set Float32Regs:$dst,
|
||||
(fma Float32Regs:$a, fpimm:$b, Float32Regs:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
def rii : NVPTXInst<(outs Float32Regs:$dst),
|
||||
(ins Float32Regs:$a, f32imm:$b, f32imm:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float32Regs:$dst, (fadd
|
||||
(fmul Float32Regs:$a, fpimm:$b), fpimm:$c))]>,
|
||||
[(set Float32Regs:$dst,
|
||||
(fma Float32Regs:$a, fpimm:$b, fpimm:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
}
|
||||
|
||||
@ -849,73 +895,32 @@ multiclass FPCONTRACT64<string OpcStr, Predicate Pred> {
|
||||
def rrr : NVPTXInst<(outs Float64Regs:$dst),
|
||||
(ins Float64Regs:$a, Float64Regs:$b, Float64Regs:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float64Regs:$dst, (fadd
|
||||
(fmul Float64Regs:$a, Float64Regs:$b),
|
||||
Float64Regs:$c))]>, Requires<[Pred]>;
|
||||
[(set Float64Regs:$dst,
|
||||
(fma Float64Regs:$a, Float64Regs:$b, Float64Regs:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
def rri : NVPTXInst<(outs Float64Regs:$dst),
|
||||
(ins Float64Regs:$a, Float64Regs:$b, f64imm:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float64Regs:$dst, (fadd (fmul Float64Regs:$a,
|
||||
Float64Regs:$b), fpimm:$c))]>, Requires<[Pred]>;
|
||||
[(set Float64Regs:$dst,
|
||||
(fma Float64Regs:$a, Float64Regs:$b, fpimm:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
def rir : NVPTXInst<(outs Float64Regs:$dst),
|
||||
(ins Float64Regs:$a, f64imm:$b, Float64Regs:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float64Regs:$dst, (fadd
|
||||
(fmul Float64Regs:$a, fpimm:$b), Float64Regs:$c))]>,
|
||||
[(set Float64Regs:$dst,
|
||||
(fma Float64Regs:$a, fpimm:$b, Float64Regs:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
def rii : NVPTXInst<(outs Float64Regs:$dst),
|
||||
(ins Float64Regs:$a, f64imm:$b, f64imm:$c),
|
||||
!strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
|
||||
[(set Float64Regs:$dst, (fadd
|
||||
(fmul Float64Regs:$a, fpimm:$b), fpimm:$c))]>,
|
||||
[(set Float64Regs:$dst,
|
||||
(fma Float64Regs:$a, fpimm:$b, fpimm:$c))]>,
|
||||
Requires<[Pred]>;
|
||||
}
|
||||
|
||||
// Due to a unknown reason (most likely a bug in tablegen), tablegen does not
|
||||
// automatically generate the rrr2 rule from
|
||||
// the rrr rule (see FPCONTRACT32) for FMA32, though it does for FMAD32.
|
||||
// If we reverse the order of the following two lines, then rrr2 rule will be
|
||||
// generated for FMA32, but not for rrr.
|
||||
// Therefore, we manually write the rrr2 rule in FPCONTRACT32.
|
||||
defm FMA32_ftz : FPCONTRACT32<"fma.rn.ftz.f32", doFMAF32_ftz>;
|
||||
defm FMA32 : FPCONTRACT32<"fma.rn.f32", doFMAF32>;
|
||||
defm FMA64 : FPCONTRACT64<"fma.rn.f64", doFMAF64>;
|
||||
|
||||
// b*c-a => fmad(b, c, -a)
|
||||
multiclass FPCONTRACT32_SUB_PAT_MAD<NVPTXInst Inst, Predicate Pred> {
|
||||
def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
|
||||
(Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
|
||||
Requires<[Pred]>;
|
||||
}
|
||||
|
||||
// a-b*c => fmad(-b,c, a)
|
||||
// - legal because a-b*c <=> a+(-b*c) <=> a+(-b)*c
|
||||
// b*c-a => fmad(b, c, -a)
|
||||
// - legal because b*c-a <=> b*c+(-a)
|
||||
multiclass FPCONTRACT32_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
|
||||
def : Pat<(fsub Float32Regs:$a, (fmul Float32Regs:$b, Float32Regs:$c)),
|
||||
(Inst (FNEGf32 Float32Regs:$b), Float32Regs:$c, Float32Regs:$a)>,
|
||||
Requires<[Pred]>;
|
||||
def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
|
||||
(Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
|
||||
Requires<[Pred]>;
|
||||
}
|
||||
|
||||
// a-b*c => fmad(-b,c, a)
|
||||
// b*c-a => fmad(b, c, -a)
|
||||
multiclass FPCONTRACT64_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
|
||||
def : Pat<(fsub Float64Regs:$a, (fmul Float64Regs:$b, Float64Regs:$c)),
|
||||
(Inst (FNEGf64 Float64Regs:$b), Float64Regs:$c, Float64Regs:$a)>,
|
||||
Requires<[Pred]>;
|
||||
|
||||
def : Pat<(fsub (fmul Float64Regs:$b, Float64Regs:$c), Float64Regs:$a),
|
||||
(Inst Float64Regs:$b, Float64Regs:$c, (FNEGf64 Float64Regs:$a))>,
|
||||
Requires<[Pred]>;
|
||||
}
|
||||
|
||||
defm FMAF32ext_ftz : FPCONTRACT32_SUB_PAT<FMA32_ftzrrr, doFMAF32AGG_ftz>;
|
||||
defm FMAF32ext : FPCONTRACT32_SUB_PAT<FMA32rrr, doFMAF32AGG>;
|
||||
defm FMAF64ext : FPCONTRACT64_SUB_PAT<FMA64rrr, doFMAF64AGG>;
|
||||
defm FMA32_ftz : FPCONTRACT32<"fma.rn.ftz.f32", doF32FTZ>;
|
||||
defm FMA32 : FPCONTRACT32<"fma.rn.f32", doNoF32FTZ>;
|
||||
defm FMA64 : FPCONTRACT64<"fma.rn.f64", doNoF32FTZ>;
|
||||
|
||||
def SINF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
|
||||
"sin.approx.f32 \t$dst, $src;",
|
||||
|
||||
9
test/CodeGen/NVPTX/imad.ll
Normal file
9
test/CodeGen/NVPTX/imad.ll
Normal file
@ -0,0 +1,9 @@
|
||||
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
|
||||
|
||||
; CHECK: imad
|
||||
define i32 @imad(i32 %a, i32 %b, i32 %c) {
|
||||
; CHECK: mad.lo.s32
|
||||
%val0 = mul i32 %a, %b
|
||||
%val1 = add i32 %val0, %c
|
||||
ret i32 %val1
|
||||
}
|
||||
37
test/CodeGen/NVPTX/mulwide.ll
Normal file
37
test/CodeGen/NVPTX/mulwide.ll
Normal file
@ -0,0 +1,37 @@
|
||||
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
|
||||
|
||||
; CHECK: mulwide16
|
||||
define i32 @mulwide16(i16 %a, i16 %b) {
|
||||
; CHECK: mul.wide.s16
|
||||
%val0 = sext i16 %a to i32
|
||||
%val1 = sext i16 %b to i32
|
||||
%val2 = mul i32 %val0, %val1
|
||||
ret i32 %val2
|
||||
}
|
||||
|
||||
; CHECK: mulwideu16
|
||||
define i32 @mulwideu16(i16 %a, i16 %b) {
|
||||
; CHECK: mul.wide.u16
|
||||
%val0 = zext i16 %a to i32
|
||||
%val1 = zext i16 %b to i32
|
||||
%val2 = mul i32 %val0, %val1
|
||||
ret i32 %val2
|
||||
}
|
||||
|
||||
; CHECK: mulwide32
|
||||
define i64 @mulwide32(i32 %a, i32 %b) {
|
||||
; CHECK: mul.wide.s32
|
||||
%val0 = sext i32 %a to i64
|
||||
%val1 = sext i32 %b to i64
|
||||
%val2 = mul i64 %val0, %val1
|
||||
ret i64 %val2
|
||||
}
|
||||
|
||||
; CHECK: mulwideu32
|
||||
define i64 @mulwideu32(i32 %a, i32 %b) {
|
||||
; CHECK: mul.wide.u32
|
||||
%val0 = zext i32 %a to i64
|
||||
%val1 = zext i32 %b to i64
|
||||
%val2 = mul i64 %val0, %val1
|
||||
ret i64 %val2
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user