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[RDF] Cache register units for reg masks instead of recalculating them

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300702 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2017-04-19 15:10:09 +00:00
parent cfaa15d905
commit 111ac46fe7
2 changed files with 29 additions and 31 deletions
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47
lib/Target/Hexagon/RDFRegisters.cpp
View File

@ -69,6 +69,19 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
for (const MachineOperand &Op : In.operands()) for (const MachineOperand &Op : In.operands())
if (Op.isRegMask()) if (Op.isRegMask())
RegMasks.insert(Op.getRegMask()); RegMasks.insert(Op.getRegMask());
MaskInfos.resize(RegMasks.size()+1);
for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) {
BitVector PU(TRI.getNumRegUnits());
const uint32_t *MB = RegMasks.get(M);
for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
if (!(MB[i/32] & (1u << (i%32))))
continue;
for (MCRegUnitIterator U(i, &TRI); U.isValid(); ++U)
PU.set(*U);
}
MaskInfos[M].Units = PU.flip();
}
} }
RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const { RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const {
@ -201,17 +214,8 @@ bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const {
bool RegisterAggr::hasAliasOf(RegisterRef RR) const { bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
// XXX SLOW return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
const uint32_t *MB = PRI.getRegMaskBits(RR.Reg);
for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) {
if (MB[i/32] & (1u << (i%32)))
continue;
if (hasAliasOf(RegisterRef(i, LaneBitmask::getAll())))
return true;
}
return false;
}
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
std::pair<uint32_t,LaneBitmask> P = *U; std::pair<uint32_t,LaneBitmask> P = *U;
@ -224,15 +228,8 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
bool RegisterAggr::hasCoverOf(RegisterRef RR) const { bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
// XXX SLOW BitVector T(PRI.getMaskUnits(RR.Reg));
const uint32_t *MB = PRI.getRegMaskBits(RR.Reg); return T.reset(Units).none();
for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) {
if (MB[i/32] & (1u << (i%32)))
continue;
if (!hasCoverOf(RegisterRef(i, LaneBitmask::getAll())))
return false;
}
return true;
} }
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
@ -246,15 +243,7 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
RegisterAggr &RegisterAggr::insert(RegisterRef RR) { RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
BitVector PU(PRI.getTRI().getNumRegUnits()); // Preserved units. Units |= PRI.getMaskUnits(RR.Reg);
const uint32_t *MB = PRI.getRegMaskBits(RR.Reg);
for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) {
if (!(MB[i/32] & (1u << (i%32))))
continue;
for (MCRegUnitIterator U(i, &PRI.getTRI()); U.isValid(); ++U)
PU.set(*U);
}
Units |= PU.flip();
return *this; return *this;
} }

13
lib/Target/Hexagon/RDFRegisters.h
View File

@ -51,6 +51,8 @@ namespace rdf {
return F - Map.begin() + 1; return F - Map.begin() + 1;
} }
uint32_t size() const { return Map.size(); }
typedef typename std::vector<T>::const_iterator const_iterator; typedef typename std::vector<T>::const_iterator const_iterator;
const_iterator begin() const { return Map.begin(); } const_iterator begin() const { return Map.begin(); }
const_iterator end() const { return Map.end(); } const_iterator end() const { return Map.end(); }
@ -107,6 +109,9 @@ namespace rdf {
RegisterRef getRefForUnit(uint32_t U) const { RegisterRef getRefForUnit(uint32_t U) const {
return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask); return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
} }
const BitVector &getMaskUnits(RegisterId MaskId) const {
return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
}
const TargetRegisterInfo &getTRI() const { return TRI; } const TargetRegisterInfo &getTRI() const { return TRI; }
@ -118,11 +123,15 @@ namespace rdf {
RegisterId Reg = 0; RegisterId Reg = 0;
LaneBitmask Mask; LaneBitmask Mask;
}; };
struct MaskInfo {
BitVector Units;
};
const TargetRegisterInfo &TRI; const TargetRegisterInfo &TRI;
IndexedSet<const uint32_t*> RegMasks;
std::vector<RegInfo> RegInfos; std::vector<RegInfo> RegInfos;
std::vector<UnitInfo> UnitInfos; std::vector<UnitInfo> UnitInfos;
IndexedSet<const uint32_t*> RegMasks; std::vector<MaskInfo> MaskInfos;
bool aliasRR(RegisterRef RA, RegisterRef RB) const; bool aliasRR(RegisterRef RA, RegisterRef RB) const;
bool aliasRM(RegisterRef RR, RegisterRef RM) const; bool aliasRM(RegisterRef RR, RegisterRef RM) const;
@ -135,7 +144,7 @@ namespace rdf {
: Units(pri.getTRI().getNumRegUnits()), PRI(pri) {} : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
RegisterAggr(const RegisterAggr &RG) = default; RegisterAggr(const RegisterAggr &RG) = default;
bool empty() const { return Units.empty(); } bool empty() const { return Units.none(); }
bool hasAliasOf(RegisterRef RR) const; bool hasAliasOf(RegisterRef RR) const;
bool hasCoverOf(RegisterRef RR) const; bool hasCoverOf(RegisterRef RR) const;
static bool isCoverOf(RegisterRef RA, RegisterRef RB, static bool isCoverOf(RegisterRef RA, RegisterRef RB,