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[PPC64] Add support for the ICBT instruction on POWER8.
Patch by Kit Barton. Support for the ICBT instruction is currently present, but limited to embedded processors. This change adds a new FeatureICBT that can be used to identify whether the ICBT instruction is available on a specific processor. Two new tests are added: * Positive test to ensure the icbt instruction is present when using -mcpu=pwr8 * Negative test to ensure the icbt instruction is not generated when using -mcpu=pwr7 Both test cases use the Prefetch opcode in LLVM. They are based on the ppc64-prefetch.ll test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226033 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt
parent
0a2caa143f
commit
11abe69e98
@ -90,8 +90,11 @@ def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
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"Enable the ldbrx instruction">;
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def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
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"Enable the cmpb instruction">;
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def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
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"Enable icbt instruction">;
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions">;
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"Enable Book E instructions",
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[FeatureICBT]>;
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def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
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"Has only the msync instruction instead of sync",
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[FeatureBookE]>;
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@ -202,12 +205,12 @@ include "PPCInstrInfo.td"
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def : Processor<"generic", G3Itineraries, [Directive32]>;
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def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
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FeatureFRES, FeatureFRSQRTE,
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FeatureBookE, FeatureMSYNC,
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DeprecatedMFTB]>;
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FeatureICBT, FeatureBookE,
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FeatureMSYNC, DeprecatedMFTB]>;
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def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
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FeatureFRES, FeatureFRSQRTE,
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FeatureBookE, FeatureMSYNC,
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DeprecatedMFTB]>;
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FeatureICBT, FeatureBookE,
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FeatureMSYNC, DeprecatedMFTB]>;
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def : Processor<"601", G3Itineraries, [Directive601]>;
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def : Processor<"602", G3Itineraries, [Directive602]>;
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def : Processor<"603", G3Itineraries, [Directive603,
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@ -247,14 +250,14 @@ def : ProcessorModel<"g5", G5Model,
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DeprecatedMFTB, DeprecatedDST]>;
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def : ProcessorModel<"e500mc", PPCE500mcModel,
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[DirectiveE500mc, FeatureMFOCRF,
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FeatureSTFIWX, FeatureBookE, FeatureISEL,
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DeprecatedMFTB]>;
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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FeatureISEL, DeprecatedMFTB]>;
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def : ProcessorModel<"e5500", PPCE5500Model,
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[DirectiveE5500, FeatureMFOCRF, Feature64Bit,
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FeatureSTFIWX, FeatureBookE, FeatureISEL,
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DeprecatedMFTB]>;
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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FeatureISEL, DeprecatedMFTB]>;
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def : ProcessorModel<"a2", PPCA2Model,
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[DirectiveA2, FeatureBookE, FeatureMFOCRF,
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[DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
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FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
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FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
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FeatureSTFIWX, FeatureLFIWAX,
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@ -262,7 +265,7 @@ def : ProcessorModel<"a2", PPCA2Model,
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FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
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/*, Feature64BitRegs */, DeprecatedMFTB]>;
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def : ProcessorModel<"a2q", PPCA2Model,
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[DirectiveA2, FeatureBookE, FeatureMFOCRF,
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[DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
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FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
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FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
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FeatureSTFIWX, FeatureLFIWAX,
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@ -319,7 +322,7 @@ def : ProcessorModel<"pwr8", P8Model,
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FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
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FeatureFPRND, FeatureFPCVT, FeatureISEL,
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FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */,
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Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
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DeprecatedMFTB, DeprecatedDST]>;
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def : Processor<"ppc", G3Itineraries, [Directive32]>;
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def : ProcessorModel<"ppc64", G5Model,
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@ -681,7 +681,7 @@ def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
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def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
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def IsE500 : Predicate<"PPCSubTarget->isE500()">;
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def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
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def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
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//===----------------------------------------------------------------------===//
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// PowerPC Multiclass Definitions.
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@ -1319,14 +1319,14 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
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PPC970_DGroup_Single;
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def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
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"icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>;
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"icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
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def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
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(DCBT xoaddr:$dst)>; // data prefetch for loads
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def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
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(DCBTST xoaddr:$dst)>; // data prefetch for stores
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def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
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(ICBT 0, xoaddr:$dst)>; // inst prefetch (for read)
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(ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
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// Atomic operations
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let usesCustomInserter = 1 in {
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@ -122,6 +122,8 @@ void PPCSubtarget::initializeEnvironment() {
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DeprecatedMFTB = false;
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DeprecatedDST = false;
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HasLazyResolverStubs = false;
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HasICBT = false;
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}
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void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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@ -113,6 +113,7 @@ protected:
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bool DeprecatedDST;
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bool HasLazyResolverStubs;
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bool IsLittleEndian;
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bool HasICBT;
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enum {
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PPC_ABI_UNKNOWN,
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@ -230,6 +231,7 @@ public:
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bool isE500() const { return IsE500; }
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bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
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bool isDeprecatedDST() const { return DeprecatedDST; }
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bool hasICBT() const { return HasICBT; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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19
test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll
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19
test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll
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@ -0,0 +1,19 @@
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; Test the ICBT instruction is not emitted on POWER7
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; Based on the ppc64-prefetch.ll test
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; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s
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declare void @llvm.prefetch(i8*, i32, i32, i32)
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define void @test(i8* %a, ...) nounwind {
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entry:
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call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0)
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ret void
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; FIXME: Crashing is not really the correct behavior here, we really should just emit nothing
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; CHECK: Cannot select: 0x{{[0-9,a-f]+}}: ch = Prefetch
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; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<0>
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; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<3>
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; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<0>
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}
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16
test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll
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16
test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll
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@ -0,0 +1,16 @@
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; Test the ICBT instruction on POWER8
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; Copied from the ppc64-prefetch.ll test
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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declare void @llvm.prefetch(i8*, i32, i32, i32)
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define void @test(i8* %a, ...) nounwind {
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entry:
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call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0)
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ret void
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; CHECK-LABEL: @test
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; CHECK: icbt
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}
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