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Add patterns for the x86 popcnt instruction.
- Also adds a new POPCNT subtarget feature that is currently enabled if the target supports SSE4.2 (nehalem) or SSE4A (barcelona). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
parent
a6091be84c
commit
1292c22645
@ -23,6 +23,9 @@ include "llvm/Target/Target.td"
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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@ -45,7 +48,7 @@ def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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[FeatureSSE41, FeaturePOPCNT]>;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions">;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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@ -63,7 +66,8 @@ def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
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"IsUAMemFast", "true",
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"Fast unaligned memory access">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions">;
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"Support SSE 4a instructions",
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[FeaturePOPCNT]>;
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def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
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"Enable AVX instructions">;
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@ -285,21 +285,27 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FREM , MVT::f80 , Expand);
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setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
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}
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if (Subtarget->hasPOPCNT()) {
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setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
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} else {
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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if (Subtarget->is64Bit())
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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}
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setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
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setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
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@ -4603,22 +4603,25 @@ defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
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//===----------------------------------------------------------------------===//
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def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
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let mayLoad = 1 in
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"popcnt{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
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def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
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"popcnt{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
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def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
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let mayLoad = 1 in
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"popcnt{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (ctpop GR32:$src))]>, XS;
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def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
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"popcnt{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
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def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
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let mayLoad = 1 in
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"popcnt{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (ctpop GR64:$src))]>, XS;
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def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
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"popcnt{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
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@ -65,6 +65,9 @@ protected:
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///
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bool HasX86_64;
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/// HasPOPCNT - True if the processor supports POPCNT.
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bool HasPOPCNT;
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/// HasSSE4A - True if the processor supports SSE4A instructions.
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bool HasSSE4A;
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@ -150,6 +153,7 @@ public:
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bool hasSSE4A() const { return HasSSE4A; }
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bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool hasPOPCNT() const { return HasPOPCNT; }
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bool hasAVX() const { return HasAVX; }
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bool hasAES() const { return HasAES; }
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bool hasCLMUL() const { return HasCLMUL; }
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38
test/CodeGen/X86/popcnt.ll
Normal file
38
test/CodeGen/X86/popcnt.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llc -march=x86-64 -mattr=+popcnt < %s | FileCheck %s
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define i8 @cnt8(i8 %x) nounwind readnone {
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%cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
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ret i8 %cnt
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; CHECK: cnt8:
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; CHECK: popcntw
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; CHECK: ret
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}
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define i16 @cnt16(i16 %x) nounwind readnone {
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%cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
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ret i16 %cnt
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; CHECK: cnt16:
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; CHECK: popcntw
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; CHECK: ret
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}
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define i32 @cnt32(i32 %x) nounwind readnone {
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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; CHECK: cnt32:
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; CHECK: popcntl
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; CHECK: ret
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}
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define i64 @cnt64(i64 %x) nounwind readnone {
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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; CHECK: cnt64:
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; CHECK: popcntq
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; CHECK: ret
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}
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declare i8 @llvm.ctpop.i8(i8) nounwind readnone
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declare i16 @llvm.ctpop.i16(i16) nounwind readnone
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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