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T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-08-14 03:18:29 +00:00
parent 865287de4a
commit 136e491280
1 changed files with 1 additions and 1 deletions
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2
lib/Target/ARM/ARMInstrThumb2.td
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@ -275,7 +275,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
// register
def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
opc, "\t$dst, $rhs, $lhs",
[(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;