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Expand pseudo/macro BteqzT8SltuX16 . There is no test case because

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at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175419 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2013-02-18 04:55:38 +00:00
parent dabfebb5c6
commit 139748f1c1
2 changed files with 7 additions and 0 deletions
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5
lib/Target/Mips/Mips16InstrInfo.cpp
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@ -142,6 +142,11 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
case Mips::BteqzT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
break;
case Mips::BteqzT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
break;
case Mips::BtnezT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
break;

2
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -1012,6 +1012,8 @@ def SltCCRxRy16: FCCRR16_ins<"slt">;
// Purpose: Set on Less Than Unsigned
// To record the result of an unsigned less-than comparison.
//
def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>;
def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
let isCodeGenOnly=1;
}