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1. introduce MipsPat in place of Pat in order to exclude those from
being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158470 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
6b0cd9b9c6
commit
1418045472
@ -230,47 +230,49 @@ def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
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// extended loads
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : Pat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
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def : Pat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
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def : Pat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>;
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def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64 addr:$src)>;
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def : Pat<(i64 (extloadi32_a addr:$src)), (LW64 addr:$src)>;
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def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>;
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def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>;
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_u addr:$src)), (ULH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_a addr:$src)), (LW64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>;
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def : MipsPat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : Pat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
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def : Pat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
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def : Pat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>;
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def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64_P8 addr:$src)>;
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def : Pat<(i64 (extloadi32_a addr:$src)), (LW64_P8 addr:$src)>;
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def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64_P8 addr:$src)>;
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def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>;
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi16_u addr:$src)), (ULH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_a addr:$src)), (LW64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32_u addr:$src)), (ULW64_P8 addr:$src)>;
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def : MipsPat<(zextloadi32_u addr:$a),
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(DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>;
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}
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// hi/lo relocs
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def : Pat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
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def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
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def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
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def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
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def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
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def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
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def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
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def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
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def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
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def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
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def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
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def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
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def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
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def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
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def : Pat<(MipsLo tglobaltlsaddr:$in), (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
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def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
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def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
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def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
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def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
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def : MipsPat<(MipsLo tglobaltlsaddr:$in),
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(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
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def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
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def : Pat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
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(DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
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def : Pat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
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(DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
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def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
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(DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
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def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
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(DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
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(DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
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(DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
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def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
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def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
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@ -290,21 +292,22 @@ defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
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// select MipsDynAlloc
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def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>,
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Requires<[IsN64, HasStandardEncoding]>;
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def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>,
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Requires<[IsN64, HasStandardEncoding]>;
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// truncate
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def : Pat<(i32 (trunc CPU64Regs:$src)),
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(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
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Requires<[IsN64, HasStandardEncoding]>;
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def : MipsPat<(i32 (trunc CPU64Regs:$src)),
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(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
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Requires<[IsN64, HasStandardEncoding]>;
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// 32-to-64-bit extension
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def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
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def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
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def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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// Sign extend in register
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def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>;
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def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
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(SLL64_64 CPU64Regs:$src)>;
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// bswap pattern
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def : Pat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
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// bswap MipsPattern
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def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
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@ -61,47 +61,54 @@ multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction SLTOp,
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Instruction SLTuOp, Instruction SLTiOp,
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Instruction SLTiuOp> {
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def : Pat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
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def : Pat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : Pat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<
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(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<
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(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
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def : MipsPat<
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(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
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def : MipsPat<
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(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : MipsPat<
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(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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}
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multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction XOROp> {
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def : Pat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
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def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
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}
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multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction XORiOp> {
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def : Pat<(select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
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def : MipsPat<
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(select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
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}
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multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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Instruction XOROp> {
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def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : Pat<(select CRC:$cond, DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
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def : Pat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
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def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
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def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
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}
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// Instantiation of instructions.
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def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
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let Predicates = [HasMips64, HasStandardEncoding],DecoderNamespace = "Mips64" in {
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let Predicates = [HasMips64, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
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def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
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let isCodeGenOnly = 1;
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@ -139,7 +146,8 @@ let Predicates = [NotFP64bit, HasStandardEncoding] in {
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def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
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def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
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}
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let Predicates = [IsFP64bit, HasStandardEncoding],DecoderNamespace = "Mips64" in {
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let Predicates = [IsFP64bit, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
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def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d"> {
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let isCodeGenOnly = 1;
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@ -54,10 +54,14 @@ let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, AssemblerPredicate<"FeatureFP64Bit">;
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def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, AssemblerPredicate<"!FeatureFP64Bit">;
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def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, AssemblerPredicate<"FeatureSingleFloat">;
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def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, AssemblerPredicate<"!FeatureSingleFloat">;
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def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
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AssemblerPredicate<"FeatureFP64Bit">;
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def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
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AssemblerPredicate<"!FeatureFP64Bit">;
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def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
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AssemblerPredicate<"FeatureSingleFloat">;
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def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
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AssemblerPredicate<"!FeatureSingleFloat">;
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// FP immediate patterns.
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def fpimm0 : PatLeaf<(fpimm), [{
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@ -427,46 +431,52 @@ def ExtractElementF64 :
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//===----------------------------------------------------------------------===//
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// Floating Point Patterns
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//===----------------------------------------------------------------------===//
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def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
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def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
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def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
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def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
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def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
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def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
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def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
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let Predicates = [NotFP64bit, HasStandardEncoding] in {
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def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
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def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
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def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
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def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
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def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
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(CVT_D32_W (MTC1 CPURegs:$src))>;
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def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
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(MFC1 (TRUNC_W_D32 AFGR64:$src))>;
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def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
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def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
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}
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let Predicates = [IsFP64bit, HasStandardEncoding] in {
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def : Pat<(f64 fpimm0), (DMTC1 ZERO_64)>;
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def : Pat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
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def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
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def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
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def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D64_W (MTC1 CPURegs:$src))>;
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def : Pat<(f32 (sint_to_fp CPU64Regs:$src)),
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(CVT_S_L (DMTC1 CPU64Regs:$src))>;
|
||||
def : Pat<(f64 (sint_to_fp CPU64Regs:$src)),
|
||||
(CVT_D64_L (DMTC1 CPU64Regs:$src))>;
|
||||
def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
|
||||
(CVT_D64_W (MTC1 CPURegs:$src))>;
|
||||
def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
|
||||
(CVT_S_L (DMTC1 CPU64Regs:$src))>;
|
||||
def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
|
||||
(CVT_D64_L (DMTC1 CPU64Regs:$src))>;
|
||||
|
||||
def : Pat<(i32 (fp_to_sint FGR64:$src)), (MFC1 (TRUNC_W_D64 FGR64:$src))>;
|
||||
def : Pat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
|
||||
def : Pat<(i64 (fp_to_sint FGR64:$src)), (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
|
||||
def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
|
||||
(MFC1 (TRUNC_W_D64 FGR64:$src))>;
|
||||
def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
|
||||
def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
|
||||
(DMFC1 (TRUNC_L_D64 FGR64:$src))>;
|
||||
|
||||
def : Pat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
|
||||
def : Pat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
|
||||
def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
|
||||
def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
|
||||
}
|
||||
|
||||
// Patterns for unaligned floating point loads and stores.
|
||||
let Predicates = [HasMips32r2Or64, NotN64, HasStandardEncoding] in {
|
||||
def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
|
||||
def : Pat<(store_u FGR32:$src, CPURegs:$addr),
|
||||
(SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
|
||||
def : MipsPat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
|
||||
def : MipsPat<(store_u FGR32:$src, CPURegs:$addr),
|
||||
(SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
|
||||
}
|
||||
|
||||
let Predicates = [IsN64, HasStandardEncoding] in {
|
||||
def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
|
||||
def : Pat<(store_u FGR32:$src, CPU64Regs:$addr),
|
||||
(SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;
|
||||
def : MipsPat<(f32 (load_u CPU64Regs:$addr)),
|
||||
(LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
|
||||
def : MipsPat<(store_u FGR32:$src, CPU64Regs:$addr),
|
||||
(SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;
|
||||
}
|
||||
|
||||
@ -172,6 +172,10 @@ def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
|
||||
def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
|
||||
AssemblerPredicate<"!FeatureMips16">;
|
||||
|
||||
class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
|
||||
let Predicates = [HasStandardEncoding];
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction format superclass
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -1058,67 +1062,67 @@ def INS : InsBase<4, "ins", CPURegs>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Small immediates
|
||||
def : Pat<(i32 immSExt16:$in),
|
||||
(ADDiu ZERO, imm:$in)>;
|
||||
def : Pat<(i32 immZExt16:$in),
|
||||
(ORi ZERO, imm:$in)>;
|
||||
def : Pat<(i32 immLow16Zero:$in),
|
||||
(LUi (HI16 imm:$in))>;
|
||||
def : MipsPat<(i32 immSExt16:$in),
|
||||
(ADDiu ZERO, imm:$in)>;
|
||||
def : MipsPat<(i32 immZExt16:$in),
|
||||
(ORi ZERO, imm:$in)>;
|
||||
def : MipsPat<(i32 immLow16Zero:$in),
|
||||
(LUi (HI16 imm:$in))>;
|
||||
|
||||
// Arbitrary immediates
|
||||
def : Pat<(i32 imm:$imm),
|
||||
def : MipsPat<(i32 imm:$imm),
|
||||
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
||||
|
||||
// Carry patterns
|
||||
def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
|
||||
def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
|
||||
(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
|
||||
def : Pat<(addc CPURegs:$src, immSExt16:$imm),
|
||||
(ADDiu CPURegs:$src, imm:$imm)>;
|
||||
// Carry MipsPatterns
|
||||
def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
|
||||
def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
|
||||
(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
|
||||
def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
|
||||
(ADDiu CPURegs:$src, imm:$imm)>;
|
||||
|
||||
// Call
|
||||
def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
||||
(JAL tglobaladdr:$dst)>;
|
||||
def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
|
||||
(JAL texternalsym:$dst)>;
|
||||
//def : Pat<(MipsJmpLink CPURegs:$dst),
|
||||
// (JALR CPURegs:$dst)>;
|
||||
def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
||||
(JAL tglobaladdr:$dst)>;
|
||||
def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
|
||||
(JAL texternalsym:$dst)>;
|
||||
//def : MipsPat<(MipsJmpLink CPURegs:$dst),
|
||||
// (JALR CPURegs:$dst)>;
|
||||
|
||||
// hi/lo relocs
|
||||
def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
||||
def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
|
||||
def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
|
||||
def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
|
||||
def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
|
||||
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
||||
def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
|
||||
def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
|
||||
def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
|
||||
def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
|
||||
|
||||
def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
||||
def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
|
||||
def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
|
||||
def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
|
||||
def : Pat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
|
||||
def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
||||
def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
|
||||
def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
|
||||
def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
|
||||
def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
|
||||
|
||||
def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
||||
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
||||
def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
|
||||
(ADDiu CPURegs:$hi, tblockaddress:$lo)>;
|
||||
def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
|
||||
(ADDiu CPURegs:$hi, tjumptable:$lo)>;
|
||||
def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
|
||||
(ADDiu CPURegs:$hi, tconstpool:$lo)>;
|
||||
def : Pat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
||||
(ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
|
||||
def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
||||
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
||||
def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
|
||||
(ADDiu CPURegs:$hi, tblockaddress:$lo)>;
|
||||
def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
|
||||
(ADDiu CPURegs:$hi, tjumptable:$lo)>;
|
||||
def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
|
||||
(ADDiu CPURegs:$hi, tconstpool:$lo)>;
|
||||
def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
||||
(ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
|
||||
|
||||
// gp_rel relocs
|
||||
def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
|
||||
(ADDiu CPURegs:$gp, tglobaladdr:$in)>;
|
||||
def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
|
||||
(ADDiu CPURegs:$gp, tconstpool:$in)>;
|
||||
def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
|
||||
(ADDiu CPURegs:$gp, tglobaladdr:$in)>;
|
||||
def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
|
||||
(ADDiu CPURegs:$gp, tconstpool:$in)>;
|
||||
|
||||
// wrapper_pic
|
||||
class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
|
||||
Pat<(MipsWrapper RC:$gp, node:$in),
|
||||
(ADDiuOp RC:$gp, node:$in)>;
|
||||
MipsPat<(MipsWrapper RC:$gp, node:$in),
|
||||
(ADDiuOp RC:$gp, node:$in)>;
|
||||
|
||||
def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
|
||||
def : WrapperPat<tconstpool, ADDiu, CPURegs>;
|
||||
@ -1128,58 +1132,58 @@ def : WrapperPat<tjumptable, ADDiu, CPURegs>;
|
||||
def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
|
||||
|
||||
// Mips does not have "not", so we expand our way
|
||||
def : Pat<(not CPURegs:$in),
|
||||
(NOR CPURegs:$in, ZERO)>;
|
||||
def : MipsPat<(not CPURegs:$in),
|
||||
(NOR CPURegs:$in, ZERO)>;
|
||||
|
||||
// extended loads
|
||||
let Predicates = [NotN64, HasStandardEncoding] in {
|
||||
def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
|
||||
}
|
||||
let Predicates = [IsN64, HasStandardEncoding] in {
|
||||
def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
|
||||
def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
|
||||
def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
|
||||
}
|
||||
|
||||
// peepholes
|
||||
let Predicates = [NotN64, HasStandardEncoding] in {
|
||||
def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
|
||||
def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
|
||||
def : MipsPat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
|
||||
def : MipsPat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
|
||||
}
|
||||
let Predicates = [IsN64, HasStandardEncoding] in {
|
||||
def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
|
||||
def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
|
||||
def : MipsPat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
|
||||
def : MipsPat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
|
||||
}
|
||||
|
||||
// brcond patterns
|
||||
multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
|
||||
Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
|
||||
Instruction SLTiuOp, Register ZEROReg> {
|
||||
def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
|
||||
(BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
|
||||
def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
|
||||
(BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
|
||||
(BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
|
||||
(BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
|
||||
|
||||
def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
||||
(BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
||||
(BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
||||
(BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
||||
(BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
||||
|
||||
def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
||||
def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
||||
def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
|
||||
(BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
||||
|
||||
def : Pat<(brcond RC:$cond, bb:$dst),
|
||||
(BNEOp RC:$cond, ZEROReg, bb:$dst)>;
|
||||
def : MipsPat<(brcond RC:$cond, bb:$dst),
|
||||
(BNEOp RC:$cond, ZEROReg, bb:$dst)>;
|
||||
}
|
||||
|
||||
defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
|
||||
@ -1187,39 +1191,39 @@ defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
|
||||
// setcc patterns
|
||||
multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
|
||||
Instruction SLTuOp, Register ZEROReg> {
|
||||
def : Pat<(seteq RC:$lhs, RC:$rhs),
|
||||
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
|
||||
def : Pat<(setne RC:$lhs, RC:$rhs),
|
||||
(SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
|
||||
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
|
||||
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
|
||||
def : MipsPat<(setne RC:$lhs, RC:$rhs),
|
||||
(SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
|
||||
}
|
||||
|
||||
multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
||||
def : Pat<(setle RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
|
||||
def : Pat<(setule RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
|
||||
def : MipsPat<(setle RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
|
||||
def : MipsPat<(setule RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
|
||||
}
|
||||
|
||||
multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
||||
def : Pat<(setgt RC:$lhs, RC:$rhs),
|
||||
(SLTOp RC:$rhs, RC:$lhs)>;
|
||||
def : Pat<(setugt RC:$lhs, RC:$rhs),
|
||||
(SLTuOp RC:$rhs, RC:$lhs)>;
|
||||
def : MipsPat<(setgt RC:$lhs, RC:$rhs),
|
||||
(SLTOp RC:$rhs, RC:$lhs)>;
|
||||
def : MipsPat<(setugt RC:$lhs, RC:$rhs),
|
||||
(SLTuOp RC:$rhs, RC:$lhs)>;
|
||||
}
|
||||
|
||||
multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
||||
def : Pat<(setge RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
|
||||
def : Pat<(setuge RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
|
||||
def : MipsPat<(setge RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
|
||||
def : MipsPat<(setuge RC:$lhs, RC:$rhs),
|
||||
(XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
|
||||
}
|
||||
|
||||
multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
|
||||
Instruction SLTiuOp> {
|
||||
def : Pat<(setge RC:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
|
||||
def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
|
||||
def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
|
||||
def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
|
||||
}
|
||||
|
||||
defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
|
||||
@ -1229,10 +1233,10 @@ defm : SetgePats<CPURegs, SLT, SLTu>;
|
||||
defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
|
||||
|
||||
// select MipsDynAlloc
|
||||
def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
|
||||
def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
|
||||
|
||||
// bswap pattern
|
||||
def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
|
||||
def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Support
|
||||
|
||||
@ -1,5 +1,9 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
; FIXME: Disabled temporarily because it should not have worked previously
|
||||
; and will be fixed after a subsequent patch
|
||||
; REQUIRES: disabled
|
||||
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user