From 1427abbf6b9cc366d38f696ed16b3c7ba2ff304e Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Thu, 19 Dec 2013 16:13:01 +0000 Subject: [PATCH] Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/CMakeLists.txt | 2 + .../PowerPC/Disassembler/CMakeLists.txt | 3 + lib/Target/PowerPC/Disassembler/LLVMBuild.txt | 23 + lib/Target/PowerPC/Disassembler/Makefile | 16 + .../PowerPC/Disassembler/PPCDisassembler.cpp | 293 +++ lib/Target/PowerPC/LLVMBuild.txt | 3 +- lib/Target/PowerPC/Makefile | 5 +- lib/Target/PowerPC/PPC.td | 3 + lib/Target/PowerPC/PPCInstr64Bit.td | 3 + lib/Target/PowerPC/PPCInstrFormats.td | 4 + lib/Target/PowerPC/PPCInstrInfo.td | 9 + test/MC/Disassembler/PowerPC/lit.local.cfg | 4 + .../PowerPC/ppc64-encoding-bookII.txt | 74 + .../PowerPC/ppc64-encoding-bookIII.txt | 107 + .../PowerPC/ppc64-encoding-ext.txt | 2253 +++++++++++++++++ .../PowerPC/ppc64-encoding-fp.txt | 329 +++ .../PowerPC/ppc64-encoding-vmx.txt | 509 ++++ .../Disassembler/PowerPC/ppc64-encoding.txt | 621 +++++ .../Disassembler/PowerPC/ppc64-operands.txt | 94 + 19 files changed, 4352 insertions(+), 3 deletions(-) create mode 100644 lib/Target/PowerPC/Disassembler/CMakeLists.txt create mode 100644 lib/Target/PowerPC/Disassembler/LLVMBuild.txt create mode 100644 lib/Target/PowerPC/Disassembler/Makefile create mode 100644 lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp create mode 100644 test/MC/Disassembler/PowerPC/lit.local.cfg create mode 100644 test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt create mode 100644 test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt create mode 100644 test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt create mode 100644 test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt create mode 100644 test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt create mode 100644 test/MC/Disassembler/PowerPC/ppc64-encoding.txt create mode 100644 test/MC/Disassembler/PowerPC/ppc64-operands.txt diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt index f2cb05a9d2c..ea4de63a244 100644 --- a/lib/Target/PowerPC/CMakeLists.txt +++ b/lib/Target/PowerPC/CMakeLists.txt @@ -3,6 +3,7 @@ set(LLVM_TARGET_DEFINITIONS PPC.td) tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM PPCGenCodeEmitter.inc -gen-emitter) +tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info) tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info) @@ -35,6 +36,7 @@ add_llvm_target(PowerPCCodeGen ) add_subdirectory(AsmParser) +add_subdirectory(Disassembler) add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) add_subdirectory(MCTargetDesc) diff --git a/lib/Target/PowerPC/Disassembler/CMakeLists.txt b/lib/Target/PowerPC/Disassembler/CMakeLists.txt new file mode 100644 index 00000000000..ca457df88d3 --- /dev/null +++ b/lib/Target/PowerPC/Disassembler/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_library(LLVMPowerPCDisassembler + PPCDisassembler.cpp + ) diff --git a/lib/Target/PowerPC/Disassembler/LLVMBuild.txt b/lib/Target/PowerPC/Disassembler/LLVMBuild.txt new file mode 100644 index 00000000000..7f29040eb6d --- /dev/null +++ b/lib/Target/PowerPC/Disassembler/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===-- ./lib/Target/PowerPC/Disassembler/LLVMBuild.txt ---------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = PowerPCDisassembler +parent = PowerPC +required_libraries = MC Support PowerPCDesc PowerPCInfo +add_to_library_groups = PowerPC diff --git a/lib/Target/PowerPC/Disassembler/Makefile b/lib/Target/PowerPC/Disassembler/Makefile new file mode 100644 index 00000000000..86e3b475220 --- /dev/null +++ b/lib/Target/PowerPC/Disassembler/Makefile @@ -0,0 +1,16 @@ +##===-- lib/Target/PowerPC/Disassembler/Makefile -----------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMPowerPCDisassembler + +# Hack: we need to include 'main' PPC target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp new file mode 100644 index 00000000000..1dab14b2ca8 --- /dev/null +++ b/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -0,0 +1,293 @@ +//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "PPC.h" +#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +typedef MCDisassembler::DecodeStatus DecodeStatus; + +namespace { +class PPCDisassembler : public MCDisassembler { +public: + PPCDisassembler(const MCSubtargetInfo &STI) + : MCDisassembler(STI) {} + virtual ~PPCDisassembler() {} + + // Override MCDisassembler. + virtual DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const LLVM_OVERRIDE; +}; +} // end anonymous namespace + +static MCDisassembler *createPPCDisassembler(const Target &T, + const MCSubtargetInfo &STI) { + return new PPCDisassembler(STI); +} + +extern "C" void LLVMInitializePowerPCDisassembler() { + // Register the disassembler for each target. + TargetRegistry::RegisterMCDisassembler(ThePPC32Target, + createPPCDisassembler); + TargetRegistry::RegisterMCDisassembler(ThePPC64Target, + createPPCDisassembler); + TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget, + createPPCDisassembler); +} + +// FIXME: These can be generated by TableGen from the existing register +// encoding values! + +static const unsigned CRRegs[] = { + PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, + PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 +}; + +static const unsigned CRBITRegs[] = { + PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, + PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, + PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, + PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, + PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, + PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, + PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, + PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN +}; + +static const unsigned FRegs[] = { + PPC::F0, PPC::F1, PPC::F2, PPC::F3, + PPC::F4, PPC::F5, PPC::F6, PPC::F7, + PPC::F8, PPC::F9, PPC::F10, PPC::F11, + PPC::F12, PPC::F13, PPC::F14, PPC::F15, + PPC::F16, PPC::F17, PPC::F18, PPC::F19, + PPC::F20, PPC::F21, PPC::F22, PPC::F23, + PPC::F24, PPC::F25, PPC::F26, PPC::F27, + PPC::F28, PPC::F29, PPC::F30, PPC::F31 +}; + +static const unsigned VRegs[] = { + PPC::V0, PPC::V1, PPC::V2, PPC::V3, + PPC::V4, PPC::V5, PPC::V6, PPC::V7, + PPC::V8, PPC::V9, PPC::V10, PPC::V11, + PPC::V12, PPC::V13, PPC::V14, PPC::V15, + PPC::V16, PPC::V17, PPC::V18, PPC::V19, + PPC::V20, PPC::V21, PPC::V22, PPC::V23, + PPC::V24, PPC::V25, PPC::V26, PPC::V27, + PPC::V28, PPC::V29, PPC::V30, PPC::V31 +}; + +static const unsigned GPRegs[] = { + PPC::R0, PPC::R1, PPC::R2, PPC::R3, + PPC::R4, PPC::R5, PPC::R6, PPC::R7, + PPC::R8, PPC::R9, PPC::R10, PPC::R11, + PPC::R12, PPC::R13, PPC::R14, PPC::R15, + PPC::R16, PPC::R17, PPC::R18, PPC::R19, + PPC::R20, PPC::R21, PPC::R22, PPC::R23, + PPC::R24, PPC::R25, PPC::R26, PPC::R27, + PPC::R28, PPC::R29, PPC::R30, PPC::R31 +}; + +static const unsigned GP0Regs[] = { + PPC::ZERO, PPC::R1, PPC::R2, PPC::R3, + PPC::R4, PPC::R5, PPC::R6, PPC::R7, + PPC::R8, PPC::R9, PPC::R10, PPC::R11, + PPC::R12, PPC::R13, PPC::R14, PPC::R15, + PPC::R16, PPC::R17, PPC::R18, PPC::R19, + PPC::R20, PPC::R21, PPC::R22, PPC::R23, + PPC::R24, PPC::R25, PPC::R26, PPC::R27, + PPC::R28, PPC::R29, PPC::R30, PPC::R31 +}; + +static const unsigned G8Regs[] = { + PPC::X0, PPC::X1, PPC::X2, PPC::X3, + PPC::X4, PPC::X5, PPC::X6, PPC::X7, + PPC::X8, PPC::X9, PPC::X10, PPC::X11, + PPC::X12, PPC::X13, PPC::X14, PPC::X15, + PPC::X16, PPC::X17, PPC::X18, PPC::X19, + PPC::X20, PPC::X21, PPC::X22, PPC::X23, + PPC::X24, PPC::X25, PPC::X26, PPC::X27, + PPC::X28, PPC::X29, PPC::X30, PPC::X31 +}; + +template +static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, + const unsigned (&Regs)[N]) { + assert(RegNo < N && "Invalid register number"); + Inst.addOperand(MCOperand::CreateReg(Regs[RegNo])); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, CRRegs); +} + +static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, CRBITRegs); +} + +static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, FRegs); +} + +static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, FRegs); +} + +static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VRegs); +} + +static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, GPRegs); +} + +static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, GP0Regs); +} + +static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, G8Regs); +} + +#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass +#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass + +template +static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::CreateImm(Imm)); + return MCDisassembler::Success; +} + +template +static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::CreateImm(SignExtend64(Imm))); + return MCDisassembler::Success; +} + +static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + // Decode the memri field (imm, reg), which has the low 16-bits as the + // displacement and the next 5 bits as the register #. + + uint64_t Base = Imm >> 16; + uint64_t Disp = Imm & 0xFFFF; + + assert(Base < 32 && "Invalid base register"); + + switch (Inst.getOpcode()) { + default: break; + case PPC::LBZU: + case PPC::LHAU: + case PPC::LHZU: + case PPC::LWZU: + case PPC::LFSU: + case PPC::LFDU: + // Add the tied output operand. + Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); + break; + case PPC::STBU: + case PPC::STHU: + case PPC::STWU: + case PPC::STFSU: + case PPC::STFDU: + Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); + break; + } + + Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp))); + Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); + return MCDisassembler::Success; +} + +static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + // Decode the memrix field (imm, reg), which has the low 14-bits as the + // displacement and the next 5 bits as the register #. + + uint64_t Base = Imm >> 14; + uint64_t Disp = Imm & 0x3FFF; + + assert(Base < 32 && "Invalid base register"); + + if (Inst.getOpcode() == PPC::LDU) + // Add the tied output operand. + Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); + else if (Inst.getOpcode() == PPC::STDU) + Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); + + Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2))); + Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); + return MCDisassembler::Success; +} + +static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + // The cr bit encoding is 0x80 >> cr_reg_num. + + unsigned Zeros = countTrailingZeros(Imm); + assert(Zeros < 8 && "Invalid CR bit value"); + + Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros])); + return MCDisassembler::Success; +} + +#include "PPCGenDisassemblerTables.inc" + +DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { + // Get the four bytes of the instruction. + uint8_t Bytes[4]; + Size = 4; + if (Region.readBytes(Address, Size, Bytes) == -1) { + Size = 0; + return MCDisassembler::Fail; + } + + // The instruction is big-endian encoded. + uint32_t Inst = (Bytes[0] << 24) | + (Bytes[1] << 16) | + (Bytes[2] << 8) | + (Bytes[3] << 0); + + return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); +} + diff --git a/lib/Target/PowerPC/LLVMBuild.txt b/lib/Target/PowerPC/LLVMBuild.txt index 3ddef36d071..9d173d64b94 100644 --- a/lib/Target/PowerPC/LLVMBuild.txt +++ b/lib/Target/PowerPC/LLVMBuild.txt @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -24,6 +24,7 @@ name = PowerPC parent = Target has_asmparser = 1 has_asmprinter = 1 +has_disassembler = 1 has_jit = 1 [component_1] diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile index 21fdcd9350e..c96674809b0 100644 --- a/lib/Target/PowerPC/Makefile +++ b/lib/Target/PowerPC/Makefile @@ -16,8 +16,9 @@ BUILT_SOURCES = PPCGenRegisterInfo.inc PPCGenAsmMatcher.inc \ PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \ PPCGenInstrInfo.inc PPCGenDAGISel.inc \ PPCGenSubtargetInfo.inc PPCGenCallingConv.inc \ - PPCGenMCCodeEmitter.inc PPCGenFastISel.inc + PPCGenMCCodeEmitter.inc PPCGenFastISel.inc \ + PPCGenDisassemblerTables.inc -DIRS = AsmParser InstPrinter TargetInfo MCTargetDesc +DIRS = AsmParser Disassembler InstPrinter TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 044740e4c75..66114983780 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -283,6 +283,9 @@ include "PPCCallingConv.td" def PPCInstrInfo : InstrInfo { let isLittleEndianEncoding = 1; + + // FIXME: Unset this when no longer needed! + let decodePositionallyEncodedOperands = 1; } def PPCAsmParser : AsmParser { diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index bfbcdf25f15..5d541502789 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -19,11 +19,13 @@ def s16imm64 : Operand { let PrintMethod = "printS16ImmOperand"; let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCS16ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<16>"; } def u16imm64 : Operand { let PrintMethod = "printU16ImmOperand"; let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCU16ImmAsmOperand; + let DecoderMethod = "decodeUImmOperand<16>"; } def s17imm64 : Operand { // This operand type is used for addis/lis to allow the assembler parser @@ -32,6 +34,7 @@ def s17imm64 : Operand { let PrintMethod = "printS16ImmOperand"; let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCS17ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<16>"; } def tocentry : Operand { let MIOperandInfo = (ops i64imm:$imm); diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index c5e179fec25..dae40c0cc26 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -14,6 +14,8 @@ class I opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : Instruction { field bits<32> Inst; + field bits<32> SoftFail = 0; + let Size = 4; bit PPC64 = 0; // Default value, override with isPPC64 @@ -67,6 +69,8 @@ class I2 opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : Instruction { field bits<64> Inst; + field bits<64> SoftFail = 0; + let Size = 8; bit PPC64 = 0; // Default value, override with isPPC64 diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index cef14f20ae0..7caa86e56b6 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -411,6 +411,7 @@ def PPCS5ImmAsmOperand : AsmOperandClass { def s5imm : Operand { let PrintMethod = "printS5ImmOperand"; let ParserMatchClass = PPCS5ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<5>"; } def PPCU5ImmAsmOperand : AsmOperandClass { let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; @@ -419,6 +420,7 @@ def PPCU5ImmAsmOperand : AsmOperandClass { def u5imm : Operand { let PrintMethod = "printU5ImmOperand"; let ParserMatchClass = PPCU5ImmAsmOperand; + let DecoderMethod = "decodeUImmOperand<5>"; } def PPCU6ImmAsmOperand : AsmOperandClass { let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; @@ -427,6 +429,7 @@ def PPCU6ImmAsmOperand : AsmOperandClass { def u6imm : Operand { let PrintMethod = "printU6ImmOperand"; let ParserMatchClass = PPCU6ImmAsmOperand; + let DecoderMethod = "decodeUImmOperand<6>"; } def PPCS16ImmAsmOperand : AsmOperandClass { let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; @@ -436,6 +439,7 @@ def s16imm : Operand { let PrintMethod = "printS16ImmOperand"; let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCS16ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<16>"; } def PPCU16ImmAsmOperand : AsmOperandClass { let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; @@ -445,6 +449,7 @@ def u16imm : Operand { let PrintMethod = "printU16ImmOperand"; let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCU16ImmAsmOperand; + let DecoderMethod = "decodeUImmOperand<16>"; } def PPCS17ImmAsmOperand : AsmOperandClass { let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; @@ -457,6 +462,7 @@ def s17imm : Operand { let PrintMethod = "printS16ImmOperand"; let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCS17ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<16>"; } def PPCDirectBrAsmOperand : AsmOperandClass { let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; @@ -502,6 +508,7 @@ def PPCCRBitMaskOperand : AsmOperandClass { def crbitm: Operand { let PrintMethod = "printcrbitm"; let EncoderMethod = "get_crbitm_encoding"; + let DecoderMethod = "decodeCRBitMOperand"; let ParserMatchClass = PPCCRBitMaskOperand; } // Address operands @@ -539,6 +546,7 @@ def memri : Operand { let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); let EncoderMethod = "getMemRIEncoding"; + let DecoderMethod = "decodeMemRIOperands"; } def memrr : Operand { let PrintMethod = "printMemRegReg"; @@ -548,6 +556,7 @@ def memrix : Operand { // memri where the imm is 4-aligned. let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); let EncoderMethod = "getMemRIXEncoding"; + let DecoderMethod = "decodeMemRIXOperands"; } // A single-register address. This is used with the SjLj diff --git a/test/MC/Disassembler/PowerPC/lit.local.cfg b/test/MC/Disassembler/PowerPC/lit.local.cfg new file mode 100644 index 00000000000..2e463005586 --- /dev/null +++ b/test/MC/Disassembler/PowerPC/lit.local.cfg @@ -0,0 +1,4 @@ +targets = set(config.root.targets_to_build.split()) +if not 'PowerPC' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt new file mode 100644 index 00000000000..5e6033d4299 --- /dev/null +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt @@ -0,0 +1,74 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s + +# CHECK: icbi 2, 3 +0x7c 0x02 0x1f 0xac + +# CHECK: dcbt 2, 3 +0x7c 0x02 0x1a 0x2c + +# CHECK: dcbtst 2, 3 +0x7c 0x02 0x19 0xec + +# CHECK: dcbz 2, 3 +0x7c 0x02 0x1f 0xec + +# CHECK: dcbst 2, 3 +0x7c 0x02 0x18 0x6c + +# CHECK: isync +0x4c 0x00 0x01 0x2c + +# CHECK: stwcx. 2, 3, 4 +0x7c 0x43 0x21 0x2d + +# CHECK: stdcx. 2, 3, 4 +0x7c 0x43 0x21 0xad + +# CHECK: sync 2 +0x7c 0x40 0x04 0xac + +# CHECK: eieio +0x7c 0x00 0x06 0xac + +# CHECK: wait 2 +0x7c 0x40 0x00 0x7c + +# CHECK: dcbf 2, 3 +0x7c 0x02 0x18 0xac + +# CHECK: lwarx 2, 3, 4 +0x7c 0x43 0x20 0x28 + +# CHECK: ldarx 2, 3, 4 +0x7c 0x43 0x20 0xa8 + +# CHECK: sync 0 +0x7c 0x00 0x04 0xac + +# CHECK: sync 0 +0x7c 0x00 0x04 0xac + +# CHECK: sync 1 +0x7c 0x20 0x04 0xac + +# CHECK: sync 2 +0x7c 0x40 0x04 0xac + +# CHECK: wait 0 +0x7c 0x00 0x00 0x7c + +# CHECK: wait 1 +0x7c 0x20 0x00 0x7c + +# CHECK: wait 2 +0x7c 0x40 0x00 0x7c + +# CHECK: mftb 2, 123 +0x7c 0x5b 0x1a 0xe6 + +# CHECK: mftb 2, 268 +0x7c 0x4c 0x42 0xe6 + +# CHECK: mftb 2, 269 +0x7c 0x4d 0x42 0xe6 + diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt new file mode 100644 index 00000000000..c5d615568cc --- /dev/null +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt @@ -0,0 +1,107 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s + +# CHECK: mtmsr 4, 0 +0x7c 0x80 0x01 0x24 + +# CHECK: mtmsr 4, 1 +0x7c 0x81 0x01 0x24 + +# CHECK: mfmsr 4 +0x7c 0x80 0x00 0xa6 + +# CHECK: mtmsrd 4, 0 +0x7c 0x80 0x01 0x64 + +# CHECK: mtmsrd 4, 1 +0x7c 0x81 0x01 0x64 + +# CHECK: mfspr 4, 272 +0x7c 0x90 0x42 0xa6 + +# CHECK: mfspr 4, 273 +0x7c 0x91 0x42 0xa6 + +# CHECK: mfspr 4, 274 +0x7c 0x92 0x42 0xa6 + +# CHECK: mfspr 4, 275 +0x7c 0x93 0x42 0xa6 + +# CHECK: mtspr 272, 4 +0x7c 0x90 0x43 0xa6 + +# CHECK: mtspr 273, 4 +0x7c 0x91 0x43 0xa6 + +# CHECK: mtspr 274, 4 +0x7c 0x92 0x43 0xa6 + +# CHECK: mtspr 275, 4 +0x7c 0x93 0x43 0xa6 + +# CHECK: mtspr 272, 4 +0x7c 0x90 0x43 0xa6 + +# CHECK: mtspr 273, 4 +0x7c 0x91 0x43 0xa6 + +# CHECK: mtspr 274, 4 +0x7c 0x92 0x43 0xa6 + +# CHECK: mtspr 275, 4 +0x7c 0x93 0x43 0xa6 + +# CHECK: mtspr 280, 4 +0x7c 0x98 0x43 0xa6 + +# CHECK: mfspr 4, 22 +0x7c 0x96 0x02 0xa6 + +# CHECK: mtspr 22, 4 +0x7c 0x96 0x03 0xa6 + +# CHECK: mfspr 4, 287 +0x7c 0x9f 0x42 0xa6 + +# CHECK: mfspr 4, 25 +0x7c 0x99 0x02 0xa6 + +# CHECK: mtspr 25, 4 +0x7c 0x99 0x03 0xa6 + +# CHECK: mfspr 4, 26 +0x7c 0x9a 0x02 0xa6 + +# CHECK: mtspr 26, 4 +0x7c 0x9a 0x03 0xa6 + +# CHECK: mfspr 4, 27 +0x7c 0x9b 0x02 0xa6 + +# CHECK: mtspr 27, 4 +0x7c 0x9b 0x03 0xa6 + +# CHECK: slbie 4 +0x7c 0x00 0x23 0x64 + +# CHECK: slbmte 4, 5 +0x7c 0x80 0x2b 0x24 + +# CHECK: slbmfee 4, 5 +0x7c 0x80 0x2f 0x26 + +# CHECK: slbia +0x7c 0x00 0x03 0xe4 + +# CHECK: tlbsync +0x7c 0x00 0x04 0x6c + +# CHECK: tlbiel 4 +0x7c 0x00 0x22 0x24 + +# CHECK: tlbie 4,0 +0x7c 0x00 0x22 0x64 + +# CHECK: tlbie 4,0 +0x7c 0x00 0x22 0x64 + diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt new file mode 100644 index 00000000000..108df30aa8c --- /dev/null +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt @@ -0,0 +1,2253 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s + +# FIXME: decode as beqlr 0 +# CHECK: bclr 12, 2, 0 +0x4d 0x82 0x00 0x20 + +# FIXME: decode as beqlr 1 +# CHECK: bclr 12, 6, 0 +0x4d 0x86 0x00 0x20 + +# FIXME: decode as beqlr 2 +# CHECK: bclr 12, 10, 0 +0x4d 0x8a 0x00 0x20 + +# FIXME: decode as beqlr 3 +# CHECK: bclr 12, 14, 0 +0x4d 0x8e 0x00 0x20 + +# FIXME: decode as beqlr 4 +# CHECK: bclr 12, 18, 0 +0x4d 0x92 0x00 0x20 + +# FIXME: decode as beqlr 5 +# CHECK: bclr 12, 22, 0 +0x4d 0x96 0x00 0x20 + +# FIXME: decode as beqlr 6 +# CHECK: bclr 12, 26, 0 +0x4d 0x9a 0x00 0x20 + +# FIXME: decode as beqlr 7 +# CHECK: bclr 12, 30, 0 +0x4d 0x9e 0x00 0x20 + +# CHECK: bclr 12, 0, 0 +0x4d 0x80 0x00 0x20 + +# CHECK: bclr 12, 1, 0 +0x4d 0x81 0x00 0x20 + +# CHECK: bclr 12, 2, 0 +0x4d 0x82 0x00 0x20 + +# CHECK: bclr 12, 3, 0 +0x4d 0x83 0x00 0x20 + +# CHECK: bclr 12, 3, 0 +0x4d 0x83 0x00 0x20 + +# CHECK: bclr 12, 4, 0 +0x4d 0x84 0x00 0x20 + +# CHECK: bclr 12, 5, 0 +0x4d 0x85 0x00 0x20 + +# CHECK: bclr 12, 6, 0 +0x4d 0x86 0x00 0x20 + +# CHECK: bclr 12, 7, 0 +0x4d 0x87 0x00 0x20 + +# CHECK: bclr 12, 7, 0 +0x4d 0x87 0x00 0x20 + +# CHECK: bclr 12, 8, 0 +0x4d 0x88 0x00 0x20 + +# CHECK: bclr 12, 9, 0 +0x4d 0x89 0x00 0x20 + +# CHECK: bclr 12, 10, 0 +0x4d 0x8a 0x00 0x20 + +# CHECK: bclr 12, 11, 0 +0x4d 0x8b 0x00 0x20 + +# CHECK: bclr 12, 11, 0 +0x4d 0x8b 0x00 0x20 + +# CHECK: bclr 12, 12, 0 +0x4d 0x8c 0x00 0x20 + +# CHECK: bclr 12, 13, 0 +0x4d 0x8d 0x00 0x20 + +# CHECK: bclr 12, 14, 0 +0x4d 0x8e 0x00 0x20 + +# CHECK: bclr 12, 15, 0 +0x4d 0x8f 0x00 0x20 + +# CHECK: bclr 12, 15, 0 +0x4d 0x8f 0x00 0x20 + +# CHECK: bclr 12, 16, 0 +0x4d 0x90 0x00 0x20 + +# CHECK: bclr 12, 17, 0 +0x4d 0x91 0x00 0x20 + +# CHECK: bclr 12, 18, 0 +0x4d 0x92 0x00 0x20 + +# CHECK: bclr 12, 19, 0 +0x4d 0x93 0x00 0x20 + +# CHECK: bclr 12, 19, 0 +0x4d 0x93 0x00 0x20 + +# CHECK: bclr 12, 20, 0 +0x4d 0x94 0x00 0x20 + +# CHECK: bclr 12, 21, 0 +0x4d 0x95 0x00 0x20 + +# CHECK: bclr 12, 22, 0 +0x4d 0x96 0x00 0x20 + +# CHECK: bclr 12, 23, 0 +0x4d 0x97 0x00 0x20 + +# CHECK: bclr 12, 23, 0 +0x4d 0x97 0x00 0x20 + +# CHECK: bclr 12, 24, 0 +0x4d 0x98 0x00 0x20 + +# CHECK: bclr 12, 25, 0 +0x4d 0x99 0x00 0x20 + +# CHECK: bclr 12, 26, 0 +0x4d 0x9a 0x00 0x20 + +# CHECK: bclr 12, 27, 0 +0x4d 0x9b 0x00 0x20 + +# CHECK: bclr 12, 27, 0 +0x4d 0x9b 0x00 0x20 + +# CHECK: bclr 12, 28, 0 +0x4d 0x9c 0x00 0x20 + +# CHECK: bclr 12, 29, 0 +0x4d 0x9d 0x00 0x20 + +# CHECK: bclr 12, 30, 0 +0x4d 0x9e 0x00 0x20 + +# CHECK: bclr 12, 31, 0 +0x4d 0x9f 0x00 0x20 + +# CHECK: bclr 12, 31, 0 +0x4d 0x9f 0x00 0x20 + +# CHECK: blr +0x4e 0x80 0x00 0x20 + +# CHECK: bctr +0x4e 0x80 0x04 0x20 + +# CHECK: blrl +0x4e 0x80 0x00 0x21 + +# CHECK: bctrl +0x4e 0x80 0x04 0x21 + +# CHECK: bclr 12, 2, 0 +0x4d 0x82 0x00 0x20 + +# CHECK: bcctr 12, 2, 0 +0x4d 0x82 0x04 0x20 + +# CHECK: bclrl 12, 2, 0 +0x4d 0x82 0x00 0x21 + +# CHECK: bcctrl 12, 2, 0 +0x4d 0x82 0x04 0x21 + +# CHECK: bclr 15, 2, 0 +0x4d 0xe2 0x00 0x20 + +# CHECK: bcctr 15, 2, 0 +0x4d 0xe2 0x04 0x20 + +# CHECK: bclrl 15, 2, 0 +0x4d 0xe2 0x00 0x21 + +# CHECK: bcctrl 15, 2, 0 +0x4d 0xe2 0x04 0x21 + +# CHECK: bclr 14, 2, 0 +0x4d 0xc2 0x00 0x20 + +# CHECK: bcctr 14, 2, 0 +0x4d 0xc2 0x04 0x20 + +# CHECK: bclrl 14, 2, 0 +0x4d 0xc2 0x00 0x21 + +# CHECK: bcctrl 14, 2, 0 +0x4d 0xc2 0x04 0x21 + +# CHECK: bclr 4, 2, 0 +0x4c 0x82 0x00 0x20 + +# CHECK: bcctr 4, 2, 0 +0x4c 0x82 0x04 0x20 + +# CHECK: bclrl 4, 2, 0 +0x4c 0x82 0x00 0x21 + +# CHECK: bcctrl 4, 2, 0 +0x4c 0x82 0x04 0x21 + +# CHECK: bclr 7, 2, 0 +0x4c 0xe2 0x00 0x20 + +# CHECK: bcctr 7, 2, 0 +0x4c 0xe2 0x04 0x20 + +# CHECK: bclrl 7, 2, 0 +0x4c 0xe2 0x00 0x21 + +# CHECK: bcctrl 7, 2, 0 +0x4c 0xe2 0x04 0x21 + +# CHECK: bclr 6, 2, 0 +0x4c 0xc2 0x00 0x20 + +# CHECK: bcctr 6, 2, 0 +0x4c 0xc2 0x04 0x20 + +# CHECK: bclrl 6, 2, 0 +0x4c 0xc2 0x00 0x21 + +# CHECK: bcctrl 6, 2, 0 +0x4c 0xc2 0x04 0x21 + +# CHECK: bdnzlr +0x4e 0x00 0x00 0x20 + +# CHECK: bdnzlrl +0x4e 0x00 0x00 0x21 + +# CHECK: bdnzlr+ +0x4f 0x20 0x00 0x20 + +# CHECK: bdnzlrl+ +0x4f 0x20 0x00 0x21 + +# CHECK: bdnzlr- +0x4f 0x00 0x00 0x20 + +# CHECK: bdnzlrl- +0x4f 0x00 0x00 0x21 + +# CHECK: bclr 8, 2, 0 +0x4d 0x02 0x00 0x20 + +# CHECK: bclrl 8, 2, 0 +0x4d 0x02 0x00 0x21 + +# CHECK: bclr 0, 2, 0 +0x4c 0x02 0x00 0x20 + +# CHECK: bclrl 0, 2, 0 +0x4c 0x02 0x00 0x21 + +# CHECK: bdzlr +0x4e 0x40 0x00 0x20 + +# CHECK: bdzlrl +0x4e 0x40 0x00 0x21 + +# CHECK: bdzlr+ +0x4f 0x60 0x00 0x20 + +# CHECK: bdzlrl+ +0x4f 0x60 0x00 0x21 + +# CHECK: bdzlr- +0x4f 0x40 0x00 0x20 + +# CHECK: bdzlrl- +0x4f 0x40 0x00 0x21 + +# CHECK: bclr 10, 2, 0 +0x4d 0x42 0x00 0x20 + +# CHECK: bclrl 10, 2, 0 +0x4d 0x42 0x00 0x21 + +# CHECK: bclr 2, 2, 0 +0x4c 0x42 0x00 0x20 + +# CHECK: bclrl 2, 2, 0 +0x4c 0x42 0x00 0x21 + +# FIXME: decode as bltlr 2 +# CHECK: bclr 12, 8, 0 +0x4d 0x88 0x00 0x20 + +# FIXME: decode as bltlr 0 +# CHECK: bclr 12, 0, 0 +0x4d 0x80 0x00 0x20 + +# FIXME: decode as bltctr 2 +# CHECK: bcctr 12, 8, 0 +0x4d 0x88 0x04 0x20 + +# FIXME: decode as bltctr 0 +# CHECK: bcctr 12, 0, 0 +0x4d 0x80 0x04 0x20 + +# FIXME: decode as bltlrl 2 +# CHECK: bclrl 12, 8, 0 +0x4d 0x88 0x00 0x21 + +# FIXME: decode as bltlrl 0 +# CHECK: bclrl 12, 0, 0 +0x4d 0x80 0x00 0x21 + +# FIXME: decode as bltctrl 2 +# CHECK: bcctrl 12, 8, 0 +0x4d 0x88 0x04 0x21 + +# FIXME: decode as bltctrl 0 +# CHECK: bcctrl 12, 0, 0 +0x4d 0x80 0x04 0x21 + +# FIXME: decode as bltlr+ 2 +# CHECK: bclr 15, 8, 0 +0x4d 0xe8 0x00 0x20 + +# FIXME: decode as bltlr+ 0 +# CHECK: bclr 15, 0, 0 +0x4d 0xe0 0x00 0x20 + +# FIXME: decode as bltctr+ 2 +# CHECK: bcctr 15, 8, 0 +0x4d 0xe8 0x04 0x20 + +# FIXME: decode as bltctr+ 0 +# CHECK: bcctr 15, 0, 0 +0x4d 0xe0 0x04 0x20 + +# FIXME: decode as bltlrl+ 2 +# CHECK: bclrl 15, 8, 0 +0x4d 0xe8 0x00 0x21 + +# FIXME: decode as bltlrl+ 0 +# CHECK: bclrl 15, 0, 0 +0x4d 0xe0 0x00 0x21 + +# FIXME: decode as bltctrl+ 2 +# CHECK: bcctrl 15, 8, 0 +0x4d 0xe8 0x04 0x21 + +# FIXME: decode as bltctrl+ 0 +# CHECK: bcctrl 15, 0, 0 +0x4d 0xe0 0x04 0x21 + +# FIXME: decode as bltlr- 2 +# CHECK: bclr 14, 8, 0 +0x4d 0xc8 0x00 0x20 + +# FIXME: decode as bltlr- 0 +# CHECK: bclr 14, 0, 0 +0x4d 0xc0 0x00 0x20 + +# FIXME: decode as bltctr- 2 +# CHECK: bcctr 14, 8, 0 +0x4d 0xc8 0x04 0x20 + +# FIXME: decode as bltctr- 0 +# CHECK: bcctr 14, 0, 0 +0x4d 0xc0 0x04 0x20 + +# FIXME: decode as bltlrl- 2 +# CHECK: bclrl 14, 8, 0 +0x4d 0xc8 0x00 0x21 + +# FIXME: decode as bltlrl- 0 +# CHECK: bclrl 14, 0, 0 +0x4d 0xc0 0x00 0x21 + +# FIXME: decode as bltctrl- 2 +# CHECK: bcctrl 14, 8, 0 +0x4d 0xc8 0x04 0x21 + +# FIXME: decode as bltctrl- 0 +# CHECK: bcctrl 14, 0, 0 +0x4d 0xc0 0x04 0x21 + +# FIXME: decode as blelr 2 +# CHECK: bclr 4, 9, 0 +0x4c 0x89 0x00 0x20 + +# FIXME: decode as blelr 0 +# CHECK: bclr 4, 1, 0 +0x4c 0x81 0x00 0x20 + +# FIXME: decode as blectr 2 +# CHECK: bcctr 4, 9, 0 +0x4c 0x89 0x04 0x20 + +# FIXME: decode as blectr 0 +# CHECK: bcctr 4, 1, 0 +0x4c 0x81 0x04 0x20 + +# FIXME: decode as blelrl 2 +# CHECK: bclrl 4, 9, 0 +0x4c 0x89 0x00 0x21 + +# FIXME: decode as blelrl 0 +# CHECK: bclrl 4, 1, 0 +0x4c 0x81 0x00 0x21 + +# FIXME: decode as blectrl 2 +# CHECK: bcctrl 4, 9, 0 +0x4c 0x89 0x04 0x21 + +# FIXME: decode as blectrl 0 +# CHECK: bcctrl 4, 1, 0 +0x4c 0x81 0x04 0x21 + +# FIXME: decode as blelr+ 2 +# CHECK: bclr 7, 9, 0 +0x4c 0xe9 0x00 0x20 + +# FIXME: decode as blelr+ 0 +# CHECK: bclr 7, 1, 0 +0x4c 0xe1 0x00 0x20 + +# FIXME: decode as blectr+ 2 +# CHECK: bcctr 7, 9, 0 +0x4c 0xe9 0x04 0x20 + +# FIXME: decode as blectr+ 0 +# CHECK: bcctr 7, 1, 0 +0x4c 0xe1 0x04 0x20 + +# FIXME: decode as blelrl+ 2 +# CHECK: bclrl 7, 9, 0 +0x4c 0xe9 0x00 0x21 + +# FIXME: decode as blelrl+ 0 +# CHECK: bclrl 7, 1, 0 +0x4c 0xe1 0x00 0x21 + +# FIXME: decode as blectrl+ 2 +# CHECK: bcctrl 7, 9, 0 +0x4c 0xe9 0x04 0x21 + +# FIXME: decode as blectrl+ 0 +# CHECK: bcctrl 7, 1, 0 +0x4c 0xe1 0x04 0x21 + +# FIXME: decode as blelr- 2 +# CHECK: bclr 6, 9, 0 +0x4c 0xc9 0x00 0x20 + +# FIXME: decode as blelr- 0 +# CHECK: bclr 6, 1, 0 +0x4c 0xc1 0x00 0x20 + +# FIXME: decode as blectr- 2 +# CHECK: bcctr 6, 9, 0 +0x4c 0xc9 0x04 0x20 + +# FIXME: decode as blectr- 0 +# CHECK: bcctr 6, 1, 0 +0x4c 0xc1 0x04 0x20 + +# FIXME: decode as blelrl- 2 +# CHECK: bclrl 6, 9, 0 +0x4c 0xc9 0x00 0x21 + +# FIXME: decode as blelrl- 0 +# CHECK: bclrl 6, 1, 0 +0x4c 0xc1 0x00 0x21 + +# FIXME: decode as blectrl- 2 +# CHECK: bcctrl 6, 9, 0 +0x4c 0xc9 0x04 0x21 + +# FIXME: decode as blectrl- 0 +# CHECK: bcctrl 6, 1, 0 +0x4c 0xc1 0x04 0x21 + +# FIXME: decode as beqlr 2 +# CHECK: bclr 12, 10, 0 +0x4d 0x8a 0x00 0x20 + +# FIXME: decode as beqlr 0 +# CHECK: bclr 12, 2, 0 +0x4d 0x82 0x00 0x20 + +# FIXME: decode as beqctr 2 +# CHECK: bcctr 12, 10, 0 +0x4d 0x8a 0x04 0x20 + +# FIXME: decode as beqctr 0 +# CHECK: bcctr 12, 2, 0 +0x4d 0x82 0x04 0x20 + +# FIXME: decode as beqlrl 2 +# CHECK: bclrl 12, 10, 0 +0x4d 0x8a 0x00 0x21 + +# FIXME: decode as beqlrl 0 +# CHECK: bclrl 12, 2, 0 +0x4d 0x82 0x00 0x21 + +# FIXME: decode as beqctrl 2 +# CHECK: bcctrl 12, 10, 0 +0x4d 0x8a 0x04 0x21 + +# FIXME: decode as beqctrl 0 +# CHECK: bcctrl 12, 2, 0 +0x4d 0x82 0x04 0x21 + +# FIXME: decode as beqlr+ 2 +# CHECK: bclr 15, 10, 0 +0x4d 0xea 0x00 0x20 + +# FIXME: decode as beqlr+ 0 +# CHECK: bclr 15, 2, 0 +0x4d 0xe2 0x00 0x20 + +# FIXME: decode as beqctr+ 2 +# CHECK: bcctr 15, 10, 0 +0x4d 0xea 0x04 0x20 + +# FIXME: decode as beqctr+ 0 +# CHECK: bcctr 15, 2, 0 +0x4d 0xe2 0x04 0x20 + +# FIXME: decode as beqlrl+ 2 +# CHECK: bclrl 15, 10, 0 +0x4d 0xea 0x00 0x21 + +# FIXME: decode as beqlrl+ 0 +# CHECK: bclrl 15, 2, 0 +0x4d 0xe2 0x00 0x21 + +# FIXME: decode as beqctrl+ 2 +# CHECK: bcctrl 15, 10, 0 +0x4d 0xea 0x04 0x21 + +# FIXME: decode as beqctrl+ 0 +# CHECK: bcctrl 15, 2, 0 +0x4d 0xe2 0x04 0x21 + +# FIXME: decode as beqlr- 2 +# CHECK: bclr 14, 10, 0 +0x4d 0xca 0x00 0x20 + +# FIXME: decode as beqlr- 0 +# CHECK: bclr 14, 2, 0 +0x4d 0xc2 0x00 0x20 + +# FIXME: decode as beqctr- 2 +# CHECK: bcctr 14, 10, 0 +0x4d 0xca 0x04 0x20 + +# FIXME: decode as beqctr- 0 +# CHECK: bcctr 14, 2, 0 +0x4d 0xc2 0x04 0x20 + +# FIXME: decode as beqlrl- 2 +# CHECK: bclrl 14, 10, 0 +0x4d 0xca 0x00 0x21 + +# FIXME: decode as beqlrl- 0 +# CHECK: bclrl 14, 2, 0 +0x4d 0xc2 0x00 0x21 + +# FIXME: decode as beqctrl- 2 +# CHECK: bcctrl 14, 10, 0 +0x4d 0xca 0x04 0x21 + +# FIXME: decode as beqctrl- 0 +# CHECK: bcctrl 14, 2, 0 +0x4d 0xc2 0x04 0x21 + +# FIXME: decode as bgelr 2 +# CHECK: bclr 4, 8, 0 +0x4c 0x88 0x00 0x20 + +# FIXME: decode as bgelr 0 +# CHECK: bclr 4, 0, 0 +0x4c 0x80 0x00 0x20 + +# FIXME: decode as bgectr 2 +# CHECK: bcctr 4, 8, 0 +0x4c 0x88 0x04 0x20 + +# FIXME: decode as bgectr 0 +# CHECK: bcctr 4, 0, 0 +0x4c 0x80 0x04 0x20 + +# FIXME: decode as bgelrl 2 +# CHECK: bclrl 4, 8, 0 +0x4c 0x88 0x00 0x21 + +# FIXME: decode as bgelrl 0 +# CHECK: bclrl 4, 0, 0 +0x4c 0x80 0x00 0x21 + +# FIXME: decode as bgectrl 2 +# CHECK: bcctrl 4, 8, 0 +0x4c 0x88 0x04 0x21 + +# FIXME: decode as bgectrl 0 +# CHECK: bcctrl 4, 0, 0 +0x4c 0x80 0x04 0x21 + +# FIXME: decode as bgelr+ 2 +# CHECK: bclr 7, 8, 0 +0x4c 0xe8 0x00 0x20 + +# FIXME: decode as bgelr+ 0 +# CHECK: bclr 7, 0, 0 +0x4c 0xe0 0x00 0x20 + +# FIXME: decode as bgectr+ 2 +# CHECK: bcctr 7, 8, 0 +0x4c 0xe8 0x04 0x20 + +# FIXME: decode as bgectr+ 0 +# CHECK: bcctr 7, 0, 0 +0x4c 0xe0 0x04 0x20 + +# FIXME: decode as bgelrl+ 2 +# CHECK: bclrl 7, 8, 0 +0x4c 0xe8 0x00 0x21 + +# FIXME: decode as bgelrl+ 0 +# CHECK: bclrl 7, 0, 0 +0x4c 0xe0 0x00 0x21 + +# FIXME: decode as bgectrl+ 2 +# CHECK: bcctrl 7, 8, 0 +0x4c 0xe8 0x04 0x21 + +# FIXME: decode as bgectrl+ 0 +# CHECK: bcctrl 7, 0, 0 +0x4c 0xe0 0x04 0x21 + +# FIXME: decode as bgelr- 2 +# CHECK: bclr 6, 8, 0 +0x4c 0xc8 0x00 0x20 + +# FIXME: decode as bgelr- 0 +# CHECK: bclr 6, 0, 0 +0x4c 0xc0 0x00 0x20 + +# FIXME: decode as bgectr- 2 +# CHECK: bcctr 6, 8, 0 +0x4c 0xc8 0x04 0x20 + +# FIXME: decode as bgectr- 0 +# CHECK: bcctr 6, 0, 0 +0x4c 0xc0 0x04 0x20 + +# FIXME: decode as bgelrl- 2 +# CHECK: bclrl 6, 8, 0 +0x4c 0xc8 0x00 0x21 + +# FIXME: decode as bgelrl- 0 +# CHECK: bclrl 6, 0, 0 +0x4c 0xc0 0x00 0x21 + +# FIXME: decode as bgectrl- 2 +# CHECK: bcctrl 6, 8, 0 +0x4c 0xc8 0x04 0x21 + +# FIXME: decode as bgectrl- 0 +# CHECK: bcctrl 6, 0, 0 +0x4c 0xc0 0x04 0x21 + +# FIXME: decode as bgtlr 2 +# CHECK: bclr 12, 9, 0 +0x4d 0x89 0x00 0x20 + +# FIXME: decode as bgtlr 0 +# CHECK: bclr 12, 1, 0 +0x4d 0x81 0x00 0x20 + +# FIXME: decode as bgtctr 2 +# CHECK: bcctr 12, 9, 0 +0x4d 0x89 0x04 0x20 + +# FIXME: decode as bgtctr 0 +# CHECK: bcctr 12, 1, 0 +0x4d 0x81 0x04 0x20 + +# FIXME: decode as bgtlrl 2 +# CHECK: bclrl 12, 9, 0 +0x4d 0x89 0x00 0x21 + +# FIXME: decode as bgtlrl 0 +# CHECK: bclrl 12, 1, 0 +0x4d 0x81 0x00 0x21 + +# FIXME: decode as bgtctrl 2 +# CHECK: bcctrl 12, 9, 0 +0x4d 0x89 0x04 0x21 + +# FIXME: decode as bgtctrl 0 +# CHECK: bcctrl 12, 1, 0 +0x4d 0x81 0x04 0x21 + +# FIXME: decode as bgtlr+ 2 +# CHECK: bclr 15, 9, 0 +0x4d 0xe9 0x00 0x20 + +# FIXME: decode as bgtlr+ 0 +# CHECK: bclr 15, 1, 0 +0x4d 0xe1 0x00 0x20 + +# FIXME: decode as bgtctr+ 2 +# CHECK: bcctr 15, 9, 0 +0x4d 0xe9 0x04 0x20 + +# FIXME: decode as bgtctr+ 0 +# CHECK: bcctr 15, 1, 0 +0x4d 0xe1 0x04 0x20 + +# FIXME: decode as bgtlrl+ 2 +# CHECK: bclrl 15, 9, 0 +0x4d 0xe9 0x00 0x21 + +# FIXME: decode as bgtlrl+ 0 +# CHECK: bclrl 15, 1, 0 +0x4d 0xe1 0x00 0x21 + +# FIXME: decode as bgtctrl+ 2 +# CHECK: bcctrl 15, 9, 0 +0x4d 0xe9 0x04 0x21 + +# FIXME: decode as bgtctrl+ 0 +# CHECK: bcctrl 15, 1, 0 +0x4d 0xe1 0x04 0x21 + +# FIXME: decode as bgtlr- 2 +# CHECK: bclr 14, 9, 0 +0x4d 0xc9 0x00 0x20 + +# FIXME: decode as bgtlr- 0 +# CHECK: bclr 14, 1, 0 +0x4d 0xc1 0x00 0x20 + +# FIXME: decode as bgtctr- 2 +# CHECK: bcctr 14, 9, 0 +0x4d 0xc9 0x04 0x20 + +# FIXME: decode as bgtctr- 0 +# CHECK: bcctr 14, 1, 0 +0x4d 0xc1 0x04 0x20 + +# FIXME: decode as bgtlrl- 2 +# CHECK: bclrl 14, 9, 0 +0x4d 0xc9 0x00 0x21 + +# FIXME: decode as bgtlrl- 0 +# CHECK: bclrl 14, 1, 0 +0x4d 0xc1 0x00 0x21 + +# FIXME: decode as bgtctrl- 2 +# CHECK: bcctrl 14, 9, 0 +0x4d 0xc9 0x04 0x21 + +# FIXME: decode as bgtctrl- 0 +# CHECK: bcctrl 14, 1, 0 +0x4d 0xc1 0x04 0x21 + +# FIXME: decode as bgelr 2 +# CHECK: bclr 4, 8, 0 +0x4c 0x88 0x00 0x20 + +# FIXME: decode as bgelr 0 +# CHECK: bclr 4, 0, 0 +0x4c 0x80 0x00 0x20 + +# FIXME: decode as bgectr 2 +# CHECK: bcctr 4, 8, 0 +0x4c 0x88 0x04 0x20 + +# FIXME: decode as bgectr 0 +# CHECK: bcctr 4, 0, 0 +0x4c 0x80 0x04 0x20 + +# FIXME: decode as bgelrl 2 +# CHECK: bclrl 4, 8, 0 +0x4c 0x88 0x00 0x21 + +# FIXME: decode as bgelrl 0 +# CHECK: bclrl 4, 0, 0 +0x4c 0x80 0x00 0x21 + +# FIXME: decode as bgectrl 2 +# CHECK: bcctrl 4, 8, 0 +0x4c 0x88 0x04 0x21 + +# FIXME: decode as bgectrl 0 +# CHECK: bcctrl 4, 0, 0 +0x4c 0x80 0x04 0x21 + +# FIXME: decode as bgelr+ 2 +# CHECK: bclr 7, 8, 0 +0x4c 0xe8 0x00 0x20 + +# FIXME: decode as bgelr+ 0 +# CHECK: bclr 7, 0, 0 +0x4c 0xe0 0x00 0x20 + +# FIXME: decode as bgectr+ 2 +# CHECK: bcctr 7, 8, 0 +0x4c 0xe8 0x04 0x20 + +# FIXME: decode as bgectr+ 0 +# CHECK: bcctr 7, 0, 0 +0x4c 0xe0 0x04 0x20 + +# FIXME: decode as bgelrl+ 2 +# CHECK: bclrl 7, 8, 0 +0x4c 0xe8 0x00 0x21 + +# FIXME: decode as bgelrl+ 0 +# CHECK: bclrl 7, 0, 0 +0x4c 0xe0 0x00 0x21 + +# FIXME: decode as bgectrl+ 2 +# CHECK: bcctrl 7, 8, 0 +0x4c 0xe8 0x04 0x21 + +# FIXME: decode as bgectrl+ 0 +# CHECK: bcctrl 7, 0, 0 +0x4c 0xe0 0x04 0x21 + +# FIXME: decode as bgelr- 2 +# CHECK: bclr 6, 8, 0 +0x4c 0xc8 0x00 0x20 + +# FIXME: decode as bgelr- 0 +# CHECK: bclr 6, 0, 0 +0x4c 0xc0 0x00 0x20 + +# FIXME: decode as bgectr- 2 +# CHECK: bcctr 6, 8, 0 +0x4c 0xc8 0x04 0x20 + +# FIXME: decode as bgectr- 0 +# CHECK: bcctr 6, 0, 0 +0x4c 0xc0 0x04 0x20 + +# FIXME: decode as bgelrl- 2 +# CHECK: bclrl 6, 8, 0 +0x4c 0xc8 0x00 0x21 + +# FIXME: decode as bgelrl- 0 +# CHECK: bclrl 6, 0, 0 +0x4c 0xc0 0x00 0x21 + +# FIXME: decode as bgectrl- 2 +# CHECK: bcctrl 6, 8, 0 +0x4c 0xc8 0x04 0x21 + +# FIXME: decode as bgectrl- 0 +# CHECK: bcctrl 6, 0, 0 +0x4c 0xc0 0x04 0x21 + +# FIXME: decode as bnelr 2 +# CHECK: bclr 4, 10, 0 +0x4c 0x8a 0x00 0x20 + +# FIXME: decode as bnelr 0 +# CHECK: bclr 4, 2, 0 +0x4c 0x82 0x00 0x20 + +# FIXME: decode as bnectr 2 +# CHECK: bcctr 4, 10, 0 +0x4c 0x8a 0x04 0x20 + +# FIXME: decode as bnectr 0 +# CHECK: bcctr 4, 2, 0 +0x4c 0x82 0x04 0x20 + +# FIXME: decode as bnelrl 2 +# CHECK: bclrl 4, 10, 0 +0x4c 0x8a 0x00 0x21 + +# FIXME: decode as bnelrl 0 +# CHECK: bclrl 4, 2, 0 +0x4c 0x82 0x00 0x21 + +# FIXME: decode as bnectrl 2 +# CHECK: bcctrl 4, 10, 0 +0x4c 0x8a 0x04 0x21 + +# FIXME: decode as bnectrl 0 +# CHECK: bcctrl 4, 2, 0 +0x4c 0x82 0x04 0x21 + +# FIXME: decode as bnelr+ 2 +# CHECK: bclr 7, 10, 0 +0x4c 0xea 0x00 0x20 + +# FIXME: decode as bnelr+ 0 +# CHECK: bclr 7, 2, 0 +0x4c 0xe2 0x00 0x20 + +# FIXME: decode as bnectr+ 2 +# CHECK: bcctr 7, 10, 0 +0x4c 0xea 0x04 0x20 + +# FIXME: decode as bnectr+ 0 +# CHECK: bcctr 7, 2, 0 +0x4c 0xe2 0x04 0x20 + +# FIXME: decode as bnelrl+ 2 +# CHECK: bclrl 7, 10, 0 +0x4c 0xea 0x00 0x21 + +# FIXME: decode as bnelrl+ 0 +# CHECK: bclrl 7, 2, 0 +0x4c 0xe2 0x00 0x21 + +# FIXME: decode as bnectrl+ 2 +# CHECK: bcctrl 7, 10, 0 +0x4c 0xea 0x04 0x21 + +# FIXME: decode as bnectrl+ 0 +# CHECK: bcctrl 7, 2, 0 +0x4c 0xe2 0x04 0x21 + +# FIXME: decode as bnelr- 2 +# CHECK: bclr 6, 10, 0 +0x4c 0xca 0x00 0x20 + +# FIXME: decode as bnelr- 0 +# CHECK: bclr 6, 2, 0 +0x4c 0xc2 0x00 0x20 + +# FIXME: decode as bnectr- 2 +# CHECK: bcctr 6, 10, 0 +0x4c 0xca 0x04 0x20 + +# FIXME: decode as bnectr- 0 +# CHECK: bcctr 6, 2, 0 +0x4c 0xc2 0x04 0x20 + +# FIXME: decode as bnelrl- 2 +# CHECK: bclrl 6, 10, 0 +0x4c 0xca 0x00 0x21 + +# FIXME: decode as bnelrl- 0 +# CHECK: bclrl 6, 2, 0 +0x4c 0xc2 0x00 0x21 + +# FIXME: decode as bnectrl- 2 +# CHECK: bcctrl 6, 10, 0 +0x4c 0xca 0x04 0x21 + +# FIXME: decode as bnectrl- 0 +# CHECK: bcctrl 6, 2, 0 +0x4c 0xc2 0x04 0x21 + +# FIXME: decode as blelr 2 +# CHECK: bclr 4, 9, 0 +0x4c 0x89 0x00 0x20 + +# FIXME: decode as blelr 0 +# CHECK: bclr 4, 1, 0 +0x4c 0x81 0x00 0x20 + +# FIXME: decode as blectr 2 +# CHECK: bcctr 4, 9, 0 +0x4c 0x89 0x04 0x20 + +# FIXME: decode as blectr 0 +# CHECK: bcctr 4, 1, 0 +0x4c 0x81 0x04 0x20 + +# FIXME: decode as blelrl 2 +# CHECK: bclrl 4, 9, 0 +0x4c 0x89 0x00 0x21 + +# FIXME: decode as blelrl 0 +# CHECK: bclrl 4, 1, 0 +0x4c 0x81 0x00 0x21 + +# FIXME: decode as blectrl 2 +# CHECK: bcctrl 4, 9, 0 +0x4c 0x89 0x04 0x21 + +# FIXME: decode as blectrl 0 +# CHECK: bcctrl 4, 1, 0 +0x4c 0x81 0x04 0x21 + +# FIXME: decode as blelr+ 2 +# CHECK: bclr 7, 9, 0 +0x4c 0xe9 0x00 0x20 + +# FIXME: decode as blelr+ 0 +# CHECK: bclr 7, 1, 0 +0x4c 0xe1 0x00 0x20 + +# FIXME: decode as blectr+ 2 +# CHECK: bcctr 7, 9, 0 +0x4c 0xe9 0x04 0x20 + +# FIXME: decode as blectr+ 0 +# CHECK: bcctr 7, 1, 0 +0x4c 0xe1 0x04 0x20 + +# FIXME: decode as blelrl+ 2 +# CHECK: bclrl 7, 9, 0 +0x4c 0xe9 0x00 0x21 + +# FIXME: decode as blelrl+ 0 +# CHECK: bclrl 7, 1, 0 +0x4c 0xe1 0x00 0x21 + +# FIXME: decode as blectrl+ 2 +# CHECK: bcctrl 7, 9, 0 +0x4c 0xe9 0x04 0x21 + +# FIXME: decode as blectrl+ 0 +# CHECK: bcctrl 7, 1, 0 +0x4c 0xe1 0x04 0x21 + +# FIXME: decode as blelr- 2 +# CHECK: bclr 6, 9, 0 +0x4c 0xc9 0x00 0x20 + +# FIXME: decode as blelr- 0 +# CHECK: bclr 6, 1, 0 +0x4c 0xc1 0x00 0x20 + +# FIXME: decode as blectr- 2 +# CHECK: bcctr 6, 9, 0 +0x4c 0xc9 0x04 0x20 + +# FIXME: decode as blectr- 0 +# CHECK: bcctr 6, 1, 0 +0x4c 0xc1 0x04 0x20 + +# FIXME: decode as blelrl- 2 +# CHECK: bclrl 6, 9, 0 +0x4c 0xc9 0x00 0x21 + +# FIXME: decode as blelrl- 0 +# CHECK: bclrl 6, 1, 0 +0x4c 0xc1 0x00 0x21 + +# FIXME: decode as blectrl- 2 +# CHECK: bcctrl 6, 9, 0 +0x4c 0xc9 0x04 0x21 + +# FIXME: decode as blectrl- 0 +# CHECK: bcctrl 6, 1, 0 +0x4c 0xc1 0x04 0x21 + +# FIXME: decode as bunlr 2 +# CHECK: bclr 12, 11, 0 +0x4d 0x8b 0x00 0x20 + +# FIXME: decode as bunlr 0 +# CHECK: bclr 12, 3, 0 +0x4d 0x83 0x00 0x20 + +# FIXME: decode as bunctr 2 +# CHECK: bcctr 12, 11, 0 +0x4d 0x8b 0x04 0x20 + +# FIXME: decode as bunctr 0 +# CHECK: bcctr 12, 3, 0 +0x4d 0x83 0x04 0x20 + +# FIXME: decode as bunlrl 2 +# CHECK: bclrl 12, 11, 0 +0x4d 0x8b 0x00 0x21 + +# FIXME: decode as bunlrl 0 +# CHECK: bclrl 12, 3, 0 +0x4d 0x83 0x00 0x21 + +# FIXME: decode as bunctrl 2 +# CHECK: bcctrl 12, 11, 0 +0x4d 0x8b 0x04 0x21 + +# FIXME: decode as bunctrl 0 +# CHECK: bcctrl 12, 3, 0 +0x4d 0x83 0x04 0x21 + +# FIXME: decode as bunlr+ 2 +# CHECK: bclr 15, 11, 0 +0x4d 0xeb 0x00 0x20 + +# FIXME: decode as bunlr+ 0 +# CHECK: bclr 15, 3, 0 +0x4d 0xe3 0x00 0x20 + +# FIXME: decode as bunctr+ 2 +# CHECK: bcctr 15, 11, 0 +0x4d 0xeb 0x04 0x20 + +# FIXME: decode as bunctr+ 0 +# CHECK: bcctr 15, 3, 0 +0x4d 0xe3 0x04 0x20 + +# FIXME: decode as bunlrl+ 2 +# CHECK: bclrl 15, 11, 0 +0x4d 0xeb 0x00 0x21 + +# FIXME: decode as bunlrl+ 0 +# CHECK: bclrl 15, 3, 0 +0x4d 0xe3 0x00 0x21 + +# FIXME: decode as bunctrl+ 2 +# CHECK: bcctrl 15, 11, 0 +0x4d 0xeb 0x04 0x21 + +# FIXME: decode as bunctrl+ 0 +# CHECK: bcctrl 15, 3, 0 +0x4d 0xe3 0x04 0x21 + +# FIXME: decode as bunlr- 2 +# CHECK: bclr 14, 11, 0 +0x4d 0xcb 0x00 0x20 + +# FIXME: decode as bunlr- 0 +# CHECK: bclr 14, 3, 0 +0x4d 0xc3 0x00 0x20 + +# FIXME: decode as bunctr- 2 +# CHECK: bcctr 14, 11, 0 +0x4d 0xcb 0x04 0x20 + +# FIXME: decode as bunctr- 0 +# CHECK: bcctr 14, 3, 0 +0x4d 0xc3 0x04 0x20 + +# FIXME: decode as bunlrl- 2 +# CHECK: bclrl 14, 11, 0 +0x4d 0xcb 0x00 0x21 + +# FIXME: decode as bunlrl- 0 +# CHECK: bclrl 14, 3, 0 +0x4d 0xc3 0x00 0x21 + +# FIXME: decode as bunctrl- 2 +# CHECK: bcctrl 14, 11, 0 +0x4d 0xcb 0x04 0x21 + +# FIXME: decode as bunctrl- 0 +# CHECK: bcctrl 14, 3, 0 +0x4d 0xc3 0x04 0x21 + +# FIXME: decode as bnulr 2 +# CHECK: bclr 4, 11, 0 +0x4c 0x8b 0x00 0x20 + +# FIXME: decode as bnulr 0 +# CHECK: bclr 4, 3, 0 +0x4c 0x83 0x00 0x20 + +# FIXME: decode as bnuctr 2 +# CHECK: bcctr 4, 11, 0 +0x4c 0x8b 0x04 0x20 + +# FIXME: decode as bnuctr 0 +# CHECK: bcctr 4, 3, 0 +0x4c 0x83 0x04 0x20 + +# FIXME: decode as bnulrl 2 +# CHECK: bclrl 4, 11, 0 +0x4c 0x8b 0x00 0x21 + +# FIXME: decode as bnulrl 0 +# CHECK: bclrl 4, 3, 0 +0x4c 0x83 0x00 0x21 + +# FIXME: decode as bnuctrl 2 +# CHECK: bcctrl 4, 11, 0 +0x4c 0x8b 0x04 0x21 + +# FIXME: decode as bnuctrl 0 +# CHECK: bcctrl 4, 3, 0 +0x4c 0x83 0x04 0x21 + +# FIXME: decode as bnulr+ 2 +# CHECK: bclr 7, 11, 0 +0x4c 0xeb 0x00 0x20 + +# FIXME: decode as bnulr+ 0 +# CHECK: bclr 7, 3, 0 +0x4c 0xe3 0x00 0x20 + +# FIXME: decode as bnuctr+ 2 +# CHECK: bcctr 7, 11, 0 +0x4c 0xeb 0x04 0x20 + +# FIXME: decode as bnuctr+ 0 +# CHECK: bcctr 7, 3, 0 +0x4c 0xe3 0x04 0x20 + +# FIXME: decode as bnulrl+ 2 +# CHECK: bclrl 7, 11, 0 +0x4c 0xeb 0x00 0x21 + +# FIXME: decode as bnulrl+ 0 +# CHECK: bclrl 7, 3, 0 +0x4c 0xe3 0x00 0x21 + +# FIXME: decode as bnuctrl+ 2 +# CHECK: bcctrl 7, 11, 0 +0x4c 0xeb 0x04 0x21 + +# FIXME: decode as bnuctrl+ 0 +# CHECK: bcctrl 7, 3, 0 +0x4c 0xe3 0x04 0x21 + +# FIXME: decode as bnulr- 2 +# CHECK: bclr 6, 11, 0 +0x4c 0xcb 0x00 0x20 + +# FIXME: decode as bnulr- 0 +# CHECK: bclr 6, 3, 0 +0x4c 0xc3 0x00 0x20 + +# FIXME: decode as bnuctr- 2 +# CHECK: bcctr 6, 11, 0 +0x4c 0xcb 0x04 0x20 + +# FIXME: decode as bnuctr- 0 +# CHECK: bcctr 6, 3, 0 +0x4c 0xc3 0x04 0x20 + +# FIXME: decode as bnulrl- 2 +# CHECK: bclrl 6, 11, 0 +0x4c 0xcb 0x00 0x21 + +# FIXME: decode as bnulrl- 0 +# CHECK: bclrl 6, 3, 0 +0x4c 0xc3 0x00 0x21 + +# FIXME: decode as bnuctrl- 2 +# CHECK: bcctrl 6, 11, 0 +0x4c 0xcb 0x04 0x21 + +# FIXME: decode as bnuctrl- 0 +# CHECK: bcctrl 6, 3, 0 +0x4c 0xc3 0x04 0x21 + +# FIXME: decode as bunlr 2 +# CHECK: bclr 12, 11, 0 +0x4d 0x8b 0x00 0x20 + +# FIXME: decode as bunlr 0 +# CHECK: bclr 12, 3, 0 +0x4d 0x83 0x00 0x20 + +# FIXME: decode as bunctr 2 +# CHECK: bcctr 12, 11, 0 +0x4d 0x8b 0x04 0x20 + +# FIXME: decode as bunctr 0 +# CHECK: bcctr 12, 3, 0 +0x4d 0x83 0x04 0x20 + +# FIXME: decode as bunlrl 2 +# CHECK: bclrl 12, 11, 0 +0x4d 0x8b 0x00 0x21 + +# FIXME: decode as bunlrl 0 +# CHECK: bclrl 12, 3, 0 +0x4d 0x83 0x00 0x21 + +# FIXME: decode as bunctrl 2 +# CHECK: bcctrl 12, 11, 0 +0x4d 0x8b 0x04 0x21 + +# FIXME: decode as bunctrl 0 +# CHECK: bcctrl 12, 3, 0 +0x4d 0x83 0x04 0x21 + +# FIXME: decode as bunlr+ 2 +# CHECK: bclr 15, 11, 0 +0x4d 0xeb 0x00 0x20 + +# FIXME: decode as bunlr+ 0 +# CHECK: bclr 15, 3, 0 +0x4d 0xe3 0x00 0x20 + +# FIXME: decode as bunctr+ 2 +# CHECK: bcctr 15, 11, 0 +0x4d 0xeb 0x04 0x20 + +# FIXME: decode as bunctr+ 0 +# CHECK: bcctr 15, 3, 0 +0x4d 0xe3 0x04 0x20 + +# FIXME: decode as bunlrl+ 2 +# CHECK: bclrl 15, 11, 0 +0x4d 0xeb 0x00 0x21 + +# FIXME: decode as bunlrl+ 0 +# CHECK: bclrl 15, 3, 0 +0x4d 0xe3 0x00 0x21 + +# FIXME: decode as bunctrl+ 2 +# CHECK: bcctrl 15, 11, 0 +0x4d 0xeb 0x04 0x21 + +# FIXME: decode as bunctrl+ 0 +# CHECK: bcctrl 15, 3, 0 +0x4d 0xe3 0x04 0x21 + +# FIXME: decode as bunlr- 2 +# CHECK: bclr 14, 11, 0 +0x4d 0xcb 0x00 0x20 + +# FIXME: decode as bunlr- 0 +# CHECK: bclr 14, 3, 0 +0x4d 0xc3 0x00 0x20 + +# FIXME: decode as bunctr- 2 +# CHECK: bcctr 14, 11, 0 +0x4d 0xcb 0x04 0x20 + +# FIXME: decode as bunctr- 0 +# CHECK: bcctr 14, 3, 0 +0x4d 0xc3 0x04 0x20 + +# FIXME: decode as bunlrl- 2 +# CHECK: bclrl 14, 11, 0 +0x4d 0xcb 0x00 0x21 + +# FIXME: decode as bunlrl- 0 +# CHECK: bclrl 14, 3, 0 +0x4d 0xc3 0x00 0x21 + +# FIXME: decode as bunctrl- 2 +# CHECK: bcctrl 14, 11, 0 +0x4d 0xcb 0x04 0x21 + +# FIXME: decode as bunctrl- 0 +# CHECK: bcctrl 14, 3, 0 +0x4d 0xc3 0x04 0x21 + +# FIXME: decode as bnulr 2 +# CHECK: bclr 4, 11, 0 +0x4c 0x8b 0x00 0x20 + +# FIXME: decode as bnulr 0 +# CHECK: bclr 4, 3, 0 +0x4c 0x83 0x00 0x20 + +# FIXME: decode as bnuctr 2 +# CHECK: bcctr 4, 11, 0 +0x4c 0x8b 0x04 0x20 + +# FIXME: decode as bnuctr 0 +# CHECK: bcctr 4, 3, 0 +0x4c 0x83 0x04 0x20 + +# FIXME: decode as bnulrl 2 +# CHECK: bclrl 4, 11, 0 +0x4c 0x8b 0x00 0x21 + +# FIXME: decode as bnulrl 0 +# CHECK: bclrl 4, 3, 0 +0x4c 0x83 0x00 0x21 + +# FIXME: decode as bnuctrl 2 +# CHECK: bcctrl 4, 11, 0 +0x4c 0x8b 0x04 0x21 + +# FIXME: decode as bnuctrl 0 +# CHECK: bcctrl 4, 3, 0 +0x4c 0x83 0x04 0x21 + +# FIXME: decode as bnulr+ 2 +# CHECK: bclr 7, 11, 0 +0x4c 0xeb 0x00 0x20 + +# FIXME: decode as bnulr+ 0 +# CHECK: bclr 7, 3, 0 +0x4c 0xe3 0x00 0x20 + +# FIXME: decode as bnuctr+ 2 +# CHECK: bcctr 7, 11, 0 +0x4c 0xeb 0x04 0x20 + +# FIXME: decode as bnuctr+ 0 +# CHECK: bcctr 7, 3, 0 +0x4c 0xe3 0x04 0x20 + +# FIXME: decode as bnulrl+ 2 +# CHECK: bclrl 7, 11, 0 +0x4c 0xeb 0x00 0x21 + +# FIXME: decode as bnulrl+ 0 +# CHECK: bclrl 7, 3, 0 +0x4c 0xe3 0x00 0x21 + +# FIXME: decode as bnuctrl+ 2 +# CHECK: bcctrl 7, 11, 0 +0x4c 0xeb 0x04 0x21 + +# FIXME: decode as bnuctrl+ 0 +# CHECK: bcctrl 7, 3, 0 +0x4c 0xe3 0x04 0x21 + +# FIXME: decode as bnulr- 2 +# CHECK: bclr 6, 11, 0 +0x4c 0xcb 0x00 0x20 + +# FIXME: decode as bnulr- 0 +# CHECK: bclr 6, 3, 0 +0x4c 0xc3 0x00 0x20 + +# FIXME: decode as bnuctr- 2 +# CHECK: bcctr 6, 11, 0 +0x4c 0xcb 0x04 0x20 + +# FIXME: decode as bnuctr- 0 +# CHECK: bcctr 6, 3, 0 +0x4c 0xc3 0x04 0x20 + +# FIXME: decode as bnulrl- 2 +# CHECK: bclrl 6, 11, 0 +0x4c 0xcb 0x00 0x21 + +# FIXME: decode as bnulrl- 0 +# CHECK: bclrl 6, 3, 0 +0x4c 0xc3 0x00 0x21 + +# FIXME: decode as bnuctrl- 2 +# CHECK: bcctrl 6, 11, 0 +0x4c 0xcb 0x04 0x21 + +# FIXME: decode as bnuctrl- 0 +# CHECK: bcctrl 6, 3, 0 +0x4c 0xc3 0x04 0x21 + +# FIXME: test bc 12, 2, target +# FIXME: test bca 12, 2, target +# FIXME: test bcl 12, 2, target +# FIXME: test bcla 12, 2, target +# FIXME: test bc 15, 2, target +# FIXME: test bca 15, 2, target +# FIXME: test bcl 15, 2, target +# FIXME: test bcla 15, 2, target +# FIXME: test bc 14, 2, target +# FIXME: test bca 14, 2, target +# FIXME: test bcl 14, 2, target +# FIXME: test bcla 14, 2, target +# FIXME: test bc 4, 2, target +# FIXME: test bca 4, 2, target +# FIXME: test bcl 4, 2, target +# FIXME: test bcla 4, 2, target +# FIXME: test bc 7, 2, target +# FIXME: test bca 7, 2, target +# FIXME: test bcl 7, 2, target +# FIXME: test bcla 7, 2, target +# FIXME: test bc 6, 2, target +# FIXME: test bca 6, 2, target +# FIXME: test bcl 6, 2, target +# FIXME: test bcla 6, 2, target +# FIXME: test bdnz target +# FIXME: test bdnza target +# FIXME: test bdnzl target +# FIXME: test bdnzla target +# FIXME: test bdnz+ target +# FIXME: test bdnza+ target +# FIXME: test bdnzl+ target +# FIXME: test bdnzla+ target +# FIXME: test bdnz- target +# FIXME: test bdnza- target +# FIXME: test bdnzl- target +# FIXME: test bdnzla- target +# FIXME: test bc 8, 2, target +# FIXME: test bca 8, 2, target +# FIXME: test bcl 8, 2, target +# FIXME: test bcla 8, 2, target +# FIXME: test bc 0, 2, target +# FIXME: test bca 0, 2, target +# FIXME: test bcl 0, 2, target +# FIXME: test bcla 0, 2, target +# FIXME: test bdz target +# FIXME: test bdza target +# FIXME: test bdzl target +# FIXME: test bdzla target +# FIXME: test bdz+ target +# FIXME: test bdza+ target +# FIXME: test bdzl+ target +# FIXME: test bdzla+ target +# FIXME: test bdz- target +# FIXME: test bdza- target +# FIXME: test bdzl- target +# FIXME: test bdzla- target +# FIXME: test bc 10, 2, target +# FIXME: test bca 10, 2, target +# FIXME: test bcl 10, 2, target +# FIXME: test bcla 10, 2, target +# FIXME: test bc 2, 2, target +# FIXME: test bca 2, 2, target +# FIXME: test bcl 2, 2, target +# FIXME: test bcla 2, 2, target +# FIXME: test blt 2, target +# FIXME: test blt 0, target +# FIXME: test blta 2, target +# FIXME: test blta 0, target +# FIXME: test bltl 2, target +# FIXME: test bltl 0, target +# FIXME: test bltla 2, target +# FIXME: test bltla 0, target +# FIXME: test blt+ 2, target +# FIXME: test blt+ 0, target +# FIXME: test blta+ 2, target +# FIXME: test blta+ 0, target +# FIXME: test bltl+ 2, target +# FIXME: test bltl+ 0, target +# FIXME: test bltla+ 2, target +# FIXME: test bltla+ 0, target +# FIXME: test blt- 2, target +# FIXME: test blt- 0, target +# FIXME: test blta- 2, target +# FIXME: test blta- 0, target +# FIXME: test bltl- 2, target +# FIXME: test bltl- 0, target +# FIXME: test bltla- 2, target +# FIXME: test bltla- 0, target +# FIXME: test ble 2, target +# FIXME: test ble 0, target +# FIXME: test blea 2, target +# FIXME: test blea 0, target +# FIXME: test blel 2, target +# FIXME: test blel 0, target +# FIXME: test blela 2, target +# FIXME: test blela 0, target +# FIXME: test ble+ 2, target +# FIXME: test ble+ 0, target +# FIXME: test blea+ 2, target +# FIXME: test blea+ 0, target +# FIXME: test blel+ 2, target +# FIXME: test blel+ 0, target +# FIXME: test blela+ 2, target +# FIXME: test blela+ 0, target +# FIXME: test ble- 2, target +# FIXME: test ble- 0, target +# FIXME: test blea- 2, target +# FIXME: test blea- 0, target +# FIXME: test blel- 2, target +# FIXME: test blel- 0, target +# FIXME: test blela- 2, target +# FIXME: test blela- 0, target +# FIXME: test beq 2, target +# FIXME: test beq 0, target +# FIXME: test beqa 2, target +# FIXME: test beqa 0, target +# FIXME: test beql 2, target +# FIXME: test beql 0, target +# FIXME: test beqla 2, target +# FIXME: test beqla 0, target +# FIXME: test beq+ 2, target +# FIXME: test beq+ 0, target +# FIXME: test beqa+ 2, target +# FIXME: test beqa+ 0, target +# FIXME: test beql+ 2, target +# FIXME: test beql+ 0, target +# FIXME: test beqla+ 2, target +# FIXME: test beqla+ 0, target +# FIXME: test beq- 2, target +# FIXME: test beq- 0, target +# FIXME: test beqa- 2, target +# FIXME: test beqa- 0, target +# FIXME: test beql- 2, target +# FIXME: test beql- 0, target +# FIXME: test beqla- 2, target +# FIXME: test beqla- 0, target +# FIXME: test bge 2, target +# FIXME: test bge 0, target +# FIXME: test bgea 2, target +# FIXME: test bgea 0, target +# FIXME: test bgel 2, target +# FIXME: test bgel 0, target +# FIXME: test bgela 2, target +# FIXME: test bgela 0, target +# FIXME: test bge+ 2, target +# FIXME: test bge+ 0, target +# FIXME: test bgea+ 2, target +# FIXME: test bgea+ 0, target +# FIXME: test bgel+ 2, target +# FIXME: test bgel+ 0, target +# FIXME: test bgela+ 2, target +# FIXME: test bgela+ 0, target +# FIXME: test bge- 2, target +# FIXME: test bge- 0, target +# FIXME: test bgea- 2, target +# FIXME: test bgea- 0, target +# FIXME: test bgel- 2, target +# FIXME: test bgel- 0, target +# FIXME: test bgela- 2, target +# FIXME: test bgela- 0, target +# FIXME: test bgt 2, target +# FIXME: test bgt 0, target +# FIXME: test bgta 2, target +# FIXME: test bgta 0, target +# FIXME: test bgtl 2, target +# FIXME: test bgtl 0, target +# FIXME: test bgtla 2, target +# FIXME: test bgtla 0, target +# FIXME: test bgt+ 2, target +# FIXME: test bgt+ 0, target +# FIXME: test bgta+ 2, target +# FIXME: test bgta+ 0, target +# FIXME: test bgtl+ 2, target +# FIXME: test bgtl+ 0, target +# FIXME: test bgtla+ 2, target +# FIXME: test bgtla+ 0, target +# FIXME: test bgt- 2, target +# FIXME: test bgt- 0, target +# FIXME: test bgta- 2, target +# FIXME: test bgta- 0, target +# FIXME: test bgtl- 2, target +# FIXME: test bgtl- 0, target +# FIXME: test bgtla- 2, target +# FIXME: test bgtla- 0, target +# FIXME: test bge 2, target +# FIXME: test bge 0, target +# FIXME: test bgea 2, target +# FIXME: test bgea 0, target +# FIXME: test bgel 2, target +# FIXME: test bgel 0, target +# FIXME: test bgela 2, target +# FIXME: test bgela 0, target +# FIXME: test bge+ 2, target +# FIXME: test bge+ 0, target +# FIXME: test bgea+ 2, target +# FIXME: test bgea+ 0, target +# FIXME: test bgel+ 2, target +# FIXME: test bgel+ 0, target +# FIXME: test bgela+ 2, target +# FIXME: test bgela+ 0, target +# FIXME: test bge- 2, target +# FIXME: test bge- 0, target +# FIXME: test bgea- 2, target +# FIXME: test bgea- 0, target +# FIXME: test bgel- 2, target +# FIXME: test bgel- 0, target +# FIXME: test bgela- 2, target +# FIXME: test bgela- 0, target +# FIXME: test bne 2, target +# FIXME: test bne 0, target +# FIXME: test bnea 2, target +# FIXME: test bnea 0, target +# FIXME: test bnel 2, target +# FIXME: test bnel 0, target +# FIXME: test bnela 2, target +# FIXME: test bnela 0, target +# FIXME: test bne+ 2, target +# FIXME: test bne+ 0, target +# FIXME: test bnea+ 2, target +# FIXME: test bnea+ 0, target +# FIXME: test bnel+ 2, target +# FIXME: test bnel+ 0, target +# FIXME: test bnela+ 2, target +# FIXME: test bnela+ 0, target +# FIXME: test bne- 2, target +# FIXME: test bne- 0, target +# FIXME: test bnea- 2, target +# FIXME: test bnea- 0, target +# FIXME: test bnel- 2, target +# FIXME: test bnel- 0, target +# FIXME: test bnela- 2, target +# FIXME: test bnela- 0, target +# FIXME: test ble 2, target +# FIXME: test ble 0, target +# FIXME: test blea 2, target +# FIXME: test blea 0, target +# FIXME: test blel 2, target +# FIXME: test blel 0, target +# FIXME: test blela 2, target +# FIXME: test blela 0, target +# FIXME: test ble+ 2, target +# FIXME: test ble+ 0, target +# FIXME: test blea+ 2, target +# FIXME: test blea+ 0, target +# FIXME: test blel+ 2, target +# FIXME: test blel+ 0, target +# FIXME: test blela+ 2, target +# FIXME: test blela+ 0, target +# FIXME: test ble- 2, target +# FIXME: test ble- 0, target +# FIXME: test blea- 2, target +# FIXME: test blea- 0, target +# FIXME: test blel- 2, target +# FIXME: test blel- 0, target +# FIXME: test blela- 2, target +# FIXME: test blela- 0, target +# FIXME: test bun 2, target +# FIXME: test bun 0, target +# FIXME: test buna 2, target +# FIXME: test buna 0, target +# FIXME: test bunl 2, target +# FIXME: test bunl 0, target +# FIXME: test bunla 2, target +# FIXME: test bunla 0, target +# FIXME: test bun+ 2, target +# FIXME: test bun+ 0, target +# FIXME: test buna+ 2, target +# FIXME: test buna+ 0, target +# FIXME: test bunl+ 2, target +# FIXME: test bunl+ 0, target +# FIXME: test bunla+ 2, target +# FIXME: test bunla+ 0, target +# FIXME: test bun- 2, target +# FIXME: test bun- 0, target +# FIXME: test buna- 2, target +# FIXME: test buna- 0, target +# FIXME: test bunl- 2, target +# FIXME: test bunl- 0, target +# FIXME: test bunla- 2, target +# FIXME: test bunla- 0, target +# FIXME: test bnu 2, target +# FIXME: test bnu 0, target +# FIXME: test bnua 2, target +# FIXME: test bnua 0, target +# FIXME: test bnul 2, target +# FIXME: test bnul 0, target +# FIXME: test bnula 2, target +# FIXME: test bnula 0, target +# FIXME: test bnu+ 2, target +# FIXME: test bnu+ 0, target +# FIXME: test bnua+ 2, target +# FIXME: test bnua+ 0, target +# FIXME: test bnul+ 2, target +# FIXME: test bnul+ 0, target +# FIXME: test bnula+ 2, target +# FIXME: test bnula+ 0, target +# FIXME: test bnu- 2, target +# FIXME: test bnu- 0, target +# FIXME: test bnua- 2, target +# FIXME: test bnua- 0, target +# FIXME: test bnul- 2, target +# FIXME: test bnul- 0, target +# FIXME: test bnula- 2, target +# FIXME: test bnula- 0, target +# FIXME: test bun 2, target +# FIXME: test bun 0, target +# FIXME: test buna 2, target +# FIXME: test buna 0, target +# FIXME: test bunl 2, target +# FIXME: test bunl 0, target +# FIXME: test bunla 2, target +# FIXME: test bunla 0, target +# FIXME: test bun+ 2, target +# FIXME: test bun+ 0, target +# FIXME: test buna+ 2, target +# FIXME: test buna+ 0, target +# FIXME: test bunl+ 2, target +# FIXME: test bunl+ 0, target +# FIXME: test bunla+ 2, target +# FIXME: test bunla+ 0, target +# FIXME: test bun- 2, target +# FIXME: test bun- 0, target +# FIXME: test buna- 2, target +# FIXME: test buna- 0, target +# FIXME: test bunl- 2, target +# FIXME: test bunl- 0, target +# FIXME: test bunla- 2, target +# FIXME: test bunla- 0, target +# FIXME: test bnu 2, target +# FIXME: test bnu 0, target +# FIXME: test bnua 2, target +# FIXME: test bnua 0, target +# FIXME: test bnul 2, target +# FIXME: test bnul 0, target +# FIXME: test bnula 2, target +# FIXME: test bnula 0, target +# FIXME: test bnu+ 2, target +# FIXME: test bnu+ 0, target +# FIXME: test bnua+ 2, target +# FIXME: test bnua+ 0, target +# FIXME: test bnul+ 2, target +# FIXME: test bnul+ 0, target +# FIXME: test bnula+ 2, target +# FIXME: test bnula+ 0, target +# FIXME: test bnu- 2, target +# FIXME: test bnu- 0, target +# FIXME: test bnua- 2, target +# FIXME: test bnua- 0, target +# FIXME: test bnul- 2, target +# FIXME: test bnul- 0, target +# FIXME: test bnula- 2, target +# FIXME: test bnula- 0, target + +# CHECK: creqv 2, 2, 2 +0x4c 0x42 0x12 0x42 + +# CHECK: crxor 2, 2, 2 +0x4c 0x42 0x11 0x82 + +# CHECK: cror 2, 3, 3 +0x4c 0x43 0x1b 0x82 + +# CHECK: crnor 2, 3, 3 +0x4c 0x43 0x18 0x42 + +# CHECK: addi 2, 3, -128 +0x38 0x43 0xff 0x80 + +# CHECK: addis 2, 3, -128 +0x3c 0x43 0xff 0x80 + +# CHECK: addic 2, 3, -128 +0x30 0x43 0xff 0x80 + +# CHECK: addic. 2, 3, -128 +0x34 0x43 0xff 0x80 + +# CHECK: subf 2, 4, 3 +0x7c 0x44 0x18 0x50 + +# CHECK: subf. 2, 4, 3 +0x7c 0x44 0x18 0x51 + +# CHECK: subfc 2, 4, 3 +0x7c 0x44 0x18 0x10 + +# CHECK: subfc. 2, 4, 3 +0x7c 0x44 0x18 0x11 + +# CHECK: cmpdi 2, 3, 128 +0x2d 0x23 0x00 0x80 + +# CHECK: cmpdi 0, 3, 128 +0x2c 0x23 0x00 0x80 + +# CHECK: cmpd 2, 3, 4 +0x7d 0x23 0x20 0x00 + +# CHECK: cmpd 0, 3, 4 +0x7c 0x23 0x20 0x00 + +# CHECK: cmpldi 2, 3, 128 +0x29 0x23 0x00 0x80 + +# CHECK: cmpldi 0, 3, 128 +0x28 0x23 0x00 0x80 + +# CHECK: cmpld 2, 3, 4 +0x7d 0x23 0x20 0x40 + +# CHECK: cmpld 0, 3, 4 +0x7c 0x23 0x20 0x40 + +# CHECK: cmpwi 2, 3, 128 +0x2d 0x03 0x00 0x80 + +# CHECK: cmpwi 0, 3, 128 +0x2c 0x03 0x00 0x80 + +# CHECK: cmpw 2, 3, 4 +0x7d 0x03 0x20 0x00 + +# CHECK: cmpw 0, 3, 4 +0x7c 0x03 0x20 0x00 + +# CHECK: cmplwi 2, 3, 128 +0x29 0x03 0x00 0x80 + +# CHECK: cmplwi 0, 3, 128 +0x28 0x03 0x00 0x80 + +# CHECK: cmplw 2, 3, 4 +0x7d 0x03 0x20 0x40 + +# CHECK: cmplw 0, 3, 4 +0x7c 0x03 0x20 0x40 + +# CHECK: twi 16, 3, 4 +0x0e 0x03 0x00 0x04 + +# CHECK: tw 16, 3, 4 +0x7e 0x03 0x20 0x08 + +# CHECK: tdi 16, 3, 4 +0x0a 0x03 0x00 0x04 + +# CHECK: td 16, 3, 4 +0x7e 0x03 0x20 0x88 + +# CHECK: twi 20, 3, 4 +0x0e 0x83 0x00 0x04 + +# CHECK: tw 20, 3, 4 +0x7e 0x83 0x20 0x08 + +# CHECK: tdi 20, 3, 4 +0x0a 0x83 0x00 0x04 + +# CHECK: td 20, 3, 4 +0x7e 0x83 0x20 0x88 + +# CHECK: twi 4, 3, 4 +0x0c 0x83 0x00 0x04 + +# CHECK: tw 4, 3, 4 +0x7c 0x83 0x20 0x08 + +# CHECK: tdi 4, 3, 4 +0x08 0x83 0x00 0x04 + +# CHECK: td 4, 3, 4 +0x7c 0x83 0x20 0x88 + +# CHECK: twi 12, 3, 4 +0x0d 0x83 0x00 0x04 + +# CHECK: tw 12, 3, 4 +0x7d 0x83 0x20 0x08 + +# CHECK: tdi 12, 3, 4 +0x09 0x83 0x00 0x04 + +# CHECK: td 12, 3, 4 +0x7d 0x83 0x20 0x88 + +# CHECK: twi 8, 3, 4 +0x0d 0x03 0x00 0x04 + +# CHECK: tw 8, 3, 4 +0x7d 0x03 0x20 0x08 + +# CHECK: tdi 8, 3, 4 +0x09 0x03 0x00 0x04 + +# CHECK: td 8, 3, 4 +0x7d 0x03 0x20 0x88 + +# CHECK: twi 12, 3, 4 +0x0d 0x83 0x00 0x04 + +# CHECK: tw 12, 3, 4 +0x7d 0x83 0x20 0x08 + +# CHECK: tdi 12, 3, 4 +0x09 0x83 0x00 0x04 + +# CHECK: td 12, 3, 4 +0x7d 0x83 0x20 0x88 + +# CHECK: twi 24, 3, 4 +0x0f 0x03 0x00 0x04 + +# CHECK: tw 24, 3, 4 +0x7f 0x03 0x20 0x08 + +# CHECK: tdi 24, 3, 4 +0x0b 0x03 0x00 0x04 + +# CHECK: td 24, 3, 4 +0x7f 0x03 0x20 0x88 + +# CHECK: twi 20, 3, 4 +0x0e 0x83 0x00 0x04 + +# CHECK: tw 20, 3, 4 +0x7e 0x83 0x20 0x08 + +# CHECK: tdi 20, 3, 4 +0x0a 0x83 0x00 0x04 + +# CHECK: td 20, 3, 4 +0x7e 0x83 0x20 0x88 + +# CHECK: twi 2, 3, 4 +0x0c 0x43 0x00 0x04 + +# CHECK: tw 2, 3, 4 +0x7c 0x43 0x20 0x08 + +# CHECK: tdi 2, 3, 4 +0x08 0x43 0x00 0x04 + +# CHECK: td 2, 3, 4 +0x7c 0x43 0x20 0x88 + +# CHECK: twi 6, 3, 4 +0x0c 0xc3 0x00 0x04 + +# CHECK: tw 6, 3, 4 +0x7c 0xc3 0x20 0x08 + +# CHECK: tdi 6, 3, 4 +0x08 0xc3 0x00 0x04 + +# CHECK: td 6, 3, 4 +0x7c 0xc3 0x20 0x88 + +# CHECK: twi 5, 3, 4 +0x0c 0xa3 0x00 0x04 + +# CHECK: tw 5, 3, 4 +0x7c 0xa3 0x20 0x08 + +# CHECK: tdi 5, 3, 4 +0x08 0xa3 0x00 0x04 + +# CHECK: td 5, 3, 4 +0x7c 0xa3 0x20 0x88 + +# CHECK: twi 1, 3, 4 +0x0c 0x23 0x00 0x04 + +# CHECK: tw 1, 3, 4 +0x7c 0x23 0x20 0x08 + +# CHECK: tdi 1, 3, 4 +0x08 0x23 0x00 0x04 + +# CHECK: td 1, 3, 4 +0x7c 0x23 0x20 0x88 + +# CHECK: twi 5, 3, 4 +0x0c 0xa3 0x00 0x04 + +# CHECK: tw 5, 3, 4 +0x7c 0xa3 0x20 0x08 + +# CHECK: tdi 5, 3, 4 +0x08 0xa3 0x00 0x04 + +# CHECK: td 5, 3, 4 +0x7c 0xa3 0x20 0x88 + +# CHECK: twi 6, 3, 4 +0x0c 0xc3 0x00 0x04 + +# CHECK: tw 6, 3, 4 +0x7c 0xc3 0x20 0x08 + +# CHECK: tdi 6, 3, 4 +0x08 0xc3 0x00 0x04 + +# CHECK: td 6, 3, 4 +0x7c 0xc3 0x20 0x88 + +# CHECK: twi 31, 3, 4 +0x0f 0xe3 0x00 0x04 + +# CHECK: tw 31, 3, 4 +0x7f 0xe3 0x20 0x08 + +# CHECK: tdi 31, 3, 4 +0x0b 0xe3 0x00 0x04 + +# CHECK: td 31, 3, 4 +0x7f 0xe3 0x20 0x88 + +# CHECK: trap +0x7f 0xe0 0x00 0x08 + +# CHECK: rldicr 2, 3, 5, 3 +0x78 0x62 0x28 0xc4 + +# CHECK: rldicr. 2, 3, 5, 3 +0x78 0x62 0x28 0xc5 + +# CHECK: rldicl 2, 3, 9, 60 +0x78 0x62 0x4f 0x20 + +# CHECK: rldicl. 2, 3, 9, 60 +0x78 0x62 0x4f 0x21 + +# CHECK: rldimi 2, 3, 55, 5 +0x78 0x62 0xb9 0x4e + +# CHECK: rldimi. 2, 3, 55, 5 +0x78 0x62 0xb9 0x4f + +# CHECK: rldicl 2, 3, 4, 0 +0x78 0x62 0x20 0x00 + +# CHECK: rldicl. 2, 3, 4, 0 +0x78 0x62 0x20 0x01 + +# CHECK: rldicl 2, 3, 60, 0 +0x78 0x62 0xe0 0x02 + +# CHECK: rldicl. 2, 3, 60, 0 +0x78 0x62 0xe0 0x03 + +# CHECK: rldcl 2, 3, 4, 0 +0x78 0x62 0x20 0x10 + +# CHECK: rldcl. 2, 3, 4, 0 +0x78 0x62 0x20 0x11 + +# CHECK: sldi 2, 3, 4 +0x78 0x62 0x26 0xe4 + +# CHECK: rldicr. 2, 3, 4, 59 +0x78 0x62 0x26 0xe5 + +# CHECK: rldicl 2, 3, 60, 4 +0x78 0x62 0xe1 0x02 + +# CHECK: rldicl. 2, 3, 60, 4 +0x78 0x62 0xe1 0x03 + +# CHECK: rldicl 2, 3, 0, 4 +0x78 0x62 0x01 0x00 + +# CHECK: rldicl. 2, 3, 0, 4 +0x78 0x62 0x01 0x01 + +# CHECK: rldicr 2, 3, 0, 59 +0x78 0x62 0x06 0xe4 + +# CHECK: rldicr. 2, 3, 0, 59 +0x78 0x62 0x06 0xe5 + +# CHECK: rldic 2, 3, 4, 1 +0x78 0x62 0x20 0x48 + +# CHECK: rldic. 2, 3, 4, 1 +0x78 0x62 0x20 0x49 + +# CHECK: rlwinm 2, 3, 5, 0, 3 +0x54 0x62 0x28 0x06 + +# CHECK: rlwinm. 2, 3, 5, 0, 3 +0x54 0x62 0x28 0x07 + +# CHECK: rlwinm 2, 3, 9, 28, 31 +0x54 0x62 0x4f 0x3e + +# CHECK: rlwinm. 2, 3, 9, 28, 31 +0x54 0x62 0x4f 0x3f + +# CHECK: rlwimi 2, 3, 27, 5, 8 +0x50 0x62 0xd9 0x50 + +# CHECK: rlwimi. 2, 3, 27, 5, 8 +0x50 0x62 0xd9 0x51 + +# CHECK: rlwimi 2, 3, 23, 5, 8 +0x50 0x62 0xb9 0x50 + +# CHECK: rlwimi. 2, 3, 23, 5, 8 +0x50 0x62 0xb9 0x51 + +# CHECK: rlwinm 2, 3, 4, 0, 31 +0x54 0x62 0x20 0x3e + +# CHECK: rlwinm. 2, 3, 4, 0, 31 +0x54 0x62 0x20 0x3f + +# CHECK: rlwinm 2, 3, 28, 0, 31 +0x54 0x62 0xe0 0x3e + +# CHECK: rlwinm. 2, 3, 28, 0, 31 +0x54 0x62 0xe0 0x3f + +# CHECK: rlwnm 2, 3, 4, 0, 31 +0x5c 0x62 0x20 0x3e + +# CHECK: rlwnm. 2, 3, 4, 0, 31 +0x5c 0x62 0x20 0x3f + +# CHECK: slwi 2, 3, 4 +0x54 0x62 0x20 0x36 + +# CHECK: rlwinm. 2, 3, 4, 0, 27 +0x54 0x62 0x20 0x37 + +# CHECK: srwi 2, 3, 4 +0x54 0x62 0xe1 0x3e + +# CHECK: rlwinm. 2, 3, 28, 4, 31 +0x54 0x62 0xe1 0x3f + +# CHECK: rlwinm 2, 3, 0, 4, 31 +0x54 0x62 0x01 0x3e + +# CHECK: rlwinm. 2, 3, 0, 4, 31 +0x54 0x62 0x01 0x3f + +# CHECK: rlwinm 2, 3, 0, 0, 27 +0x54 0x62 0x00 0x36 + +# CHECK: rlwinm. 2, 3, 0, 0, 27 +0x54 0x62 0x00 0x37 + +# CHECK: rlwinm 2, 3, 4, 1, 27 +0x54 0x62 0x20 0x76 + +# CHECK: rlwinm. 2, 3, 4, 1, 27 +0x54 0x62 0x20 0x77 + +# CHECK: mtspr 1, 2 +0x7c 0x41 0x03 0xa6 + +# CHECK: mfspr 2, 1 +0x7c 0x41 0x02 0xa6 + +# CHECK: mtlr 2 +0x7c 0x48 0x03 0xa6 + +# CHECK: mflr 2 +0x7c 0x48 0x02 0xa6 + +# CHECK: mtctr 2 +0x7c 0x49 0x03 0xa6 + +# CHECK: mfctr 2 +0x7c 0x49 0x02 0xa6 + +# CHECK: nop +0x60 0x00 0x00 0x00 + +# CHECK: xori 0, 0, 0 +0x68 0x00 0x00 0x00 + +# CHECK: li 2, 128 +0x38 0x40 0x00 0x80 + +# CHECK: lis 2, 128 +0x3c 0x40 0x00 0x80 + +# CHECK: mr 2, 3 +0x7c 0x62 0x1b 0x78 + +# CHECK: or. 2, 3, 3 +0x7c 0x62 0x1b 0x79 + +# CHECK: nor 2, 3, 3 +0x7c 0x62 0x18 0xf8 + +# CHECK: nor. 2, 3, 3 +0x7c 0x62 0x18 0xf9 + +# CHECK: mtcrf 255, 2 +0x7c 0x4f 0xf1 0x20 + diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt new file mode 100644 index 00000000000..1c01c9dcf82 --- /dev/null +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt @@ -0,0 +1,329 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s + +# CHECK: lfs 2, 128(4) +0xc0 0x44 0x00 0x80 + +# CHECK: lfsx 2, 3, 4 +0x7c 0x43 0x24 0x2e + +# CHECK: lfsu 2, 128(4) +0xc4 0x44 0x00 0x80 + +# CHECK: lfsux 2, 3, 4 +0x7c 0x43 0x24 0x6e + +# CHECK: lfd 2, 128(4) +0xc8 0x44 0x00 0x80 + +# CHECK: lfdx 2, 3, 4 +0x7c 0x43 0x24 0xae + +# CHECK: lfdu 2, 128(4) +0xcc 0x44 0x00 0x80 + +# CHECK: lfdux 2, 3, 4 +0x7c 0x43 0x24 0xee + +# CHECK: lfiwax 2, 3, 4 +0x7c 0x43 0x26 0xae + +# CHECK: lfiwzx 2, 3, 4 +0x7c 0x43 0x26 0xee + +# CHECK: stfs 2, 128(4) +0xd0 0x44 0x00 0x80 + +# CHECK: stfsx 2, 3, 4 +0x7c 0x43 0x25 0x2e + +# CHECK: stfsu 2, 128(4) +0xd4 0x44 0x00 0x80 + +# CHECK: stfsux 2, 3, 4 +0x7c 0x43 0x25 0x6e + +# CHECK: stfd 2, 128(4) +0xd8 0x44 0x00 0x80 + +# CHECK: stfdx 2, 3, 4 +0x7c 0x43 0x25 0xae + +# CHECK: stfdu 2, 128(4) +0xdc 0x44 0x00 0x80 + +# CHECK: stfdux 2, 3, 4 +0x7c 0x43 0x25 0xee + +# CHECK: stfiwx 2, 3, 4 +0x7c 0x43 0x27 0xae + +# CHECK: fmr 2, 3 +0xfc 0x40 0x18 0x90 + +# CHECK: fmr. 2, 3 +0xfc 0x40 0x18 0x91 + +# CHECK: fneg 2, 3 +0xfc 0x40 0x18 0x50 + +# CHECK: fneg. 2, 3 +0xfc 0x40 0x18 0x51 + +# CHECK: fabs 2, 3 +0xfc 0x40 0x1a 0x10 + +# CHECK: fabs. 2, 3 +0xfc 0x40 0x1a 0x11 + +# CHECK: fnabs 2, 3 +0xfc 0x40 0x19 0x10 + +# CHECK: fnabs. 2, 3 +0xfc 0x40 0x19 0x11 + +# CHECK: fcpsgn 2, 3, 4 +0xfc 0x43 0x20 0x10 + +# CHECK: fcpsgn. 2, 3, 4 +0xfc 0x43 0x20 0x11 + +# CHECK: fadd 2, 3, 4 +0xfc 0x43 0x20 0x2a + +# CHECK: fadd. 2, 3, 4 +0xfc 0x43 0x20 0x2b + +# CHECK: fadds 2, 3, 4 +0xec 0x43 0x20 0x2a + +# CHECK: fadds. 2, 3, 4 +0xec 0x43 0x20 0x2b + +# CHECK: fsub 2, 3, 4 +0xfc 0x43 0x20 0x28 + +# CHECK: fsub. 2, 3, 4 +0xfc 0x43 0x20 0x29 + +# CHECK: fsubs 2, 3, 4 +0xec 0x43 0x20 0x28 + +# CHECK: fsubs. 2, 3, 4 +0xec 0x43 0x20 0x29 + +# CHECK: fmul 2, 3, 4 +0xfc 0x43 0x01 0x32 + +# CHECK: fmul. 2, 3, 4 +0xfc 0x43 0x01 0x33 + +# CHECK: fmuls 2, 3, 4 +0xec 0x43 0x01 0x32 + +# CHECK: fmuls. 2, 3, 4 +0xec 0x43 0x01 0x33 + +# CHECK: fdiv 2, 3, 4 +0xfc 0x43 0x20 0x24 + +# CHECK: fdiv. 2, 3, 4 +0xfc 0x43 0x20 0x25 + +# CHECK: fdivs 2, 3, 4 +0xec 0x43 0x20 0x24 + +# CHECK: fdivs. 2, 3, 4 +0xec 0x43 0x20 0x25 + +# CHECK: fsqrt 2, 3 +0xfc 0x40 0x18 0x2c + +# CHECK: fsqrt. 2, 3 +0xfc 0x40 0x18 0x2d + +# CHECK: fsqrts 2, 3 +0xec 0x40 0x18 0x2c + +# CHECK: fsqrts. 2, 3 +0xec 0x40 0x18 0x2d + +# CHECK: fre 2, 3 +0xfc 0x40 0x18 0x30 + +# CHECK: fre. 2, 3 +0xfc 0x40 0x18 0x31 + +# CHECK: fres 2, 3 +0xec 0x40 0x18 0x30 + +# CHECK: fres. 2, 3 +0xec 0x40 0x18 0x31 + +# CHECK: frsqrte 2, 3 +0xfc 0x40 0x18 0x34 + +# CHECK: frsqrte. 2, 3 +0xfc 0x40 0x18 0x35 + +# CHECK: frsqrtes 2, 3 +0xec 0x40 0x18 0x34 + +# CHECK: frsqrtes. 2, 3 +0xec 0x40 0x18 0x35 + +# CHECK: fmadd 2, 3, 4, 5 +0xfc 0x43 0x29 0x3a + +# CHECK: fmadd. 2, 3, 4, 5 +0xfc 0x43 0x29 0x3b + +# CHECK: fmadds 2, 3, 4, 5 +0xec 0x43 0x29 0x3a + +# CHECK: fmadds. 2, 3, 4, 5 +0xec 0x43 0x29 0x3b + +# CHECK: fmsub 2, 3, 4, 5 +0xfc 0x43 0x29 0x38 + +# CHECK: fmsub. 2, 3, 4, 5 +0xfc 0x43 0x29 0x39 + +# CHECK: fmsubs 2, 3, 4, 5 +0xec 0x43 0x29 0x38 + +# CHECK: fmsubs. 2, 3, 4, 5 +0xec 0x43 0x29 0x39 + +# CHECK: fnmadd 2, 3, 4, 5 +0xfc 0x43 0x29 0x3e + +# CHECK: fnmadd. 2, 3, 4, 5 +0xfc 0x43 0x29 0x3f + +# CHECK: fnmadds 2, 3, 4, 5 +0xec 0x43 0x29 0x3e + +# CHECK: fnmadds. 2, 3, 4, 5 +0xec 0x43 0x29 0x3f + +# CHECK: fnmsub 2, 3, 4, 5 +0xfc 0x43 0x29 0x3c + +# CHECK: fnmsub. 2, 3, 4, 5 +0xfc 0x43 0x29 0x3d + +# CHECK: fnmsubs 2, 3, 4, 5 +0xec 0x43 0x29 0x3c + +# CHECK: fnmsubs. 2, 3, 4, 5 +0xec 0x43 0x29 0x3d + +# CHECK: frsp 2, 3 +0xfc 0x40 0x18 0x18 + +# CHECK: frsp. 2, 3 +0xfc 0x40 0x18 0x19 + +# CHECK: fctid 2, 3 +0xfc 0x40 0x1e 0x5c + +# CHECK: fctid. 2, 3 +0xfc 0x40 0x1e 0x5d + +# CHECK: fctidz 2, 3 +0xfc 0x40 0x1e 0x5e + +# CHECK: fctidz. 2, 3 +0xfc 0x40 0x1e 0x5f + +# CHECK: fctiduz 2, 3 +0xfc 0x40 0x1f 0x5e + +# CHECK: fctiduz. 2, 3 +0xfc 0x40 0x1f 0x5f + +# CHECK: fctiw 2, 3 +0xfc 0x40 0x18 0x1c + +# CHECK: fctiw. 2, 3 +0xfc 0x40 0x18 0x1d + +# CHECK: fctiwz 2, 3 +0xfc 0x40 0x18 0x1e + +# CHECK: fctiwz. 2, 3 +0xfc 0x40 0x18 0x1f + +# CHECK: fctiwuz 2, 3 +0xfc 0x40 0x19 0x1e + +# CHECK: fctiwuz. 2, 3 +0xfc 0x40 0x19 0x1f + +# CHECK: fcfid 2, 3 +0xfc 0x40 0x1e 0x9c + +# CHECK: fcfid. 2, 3 +0xfc 0x40 0x1e 0x9d + +# CHECK: fcfidu 2, 3 +0xfc 0x40 0x1f 0x9c + +# CHECK: fcfidu. 2, 3 +0xfc 0x40 0x1f 0x9d + +# CHECK: fcfids 2, 3 +0xec 0x40 0x1e 0x9c + +# CHECK: fcfids. 2, 3 +0xec 0x40 0x1e 0x9d + +# CHECK: fcfidus 2, 3 +0xec 0x40 0x1f 0x9c + +# CHECK: fcfidus. 2, 3 +0xec 0x40 0x1f 0x9d + +# CHECK: frin 2, 3 +0xfc 0x40 0x1b 0x10 + +# CHECK: frin. 2, 3 +0xfc 0x40 0x1b 0x11 + +# CHECK: frip 2, 3 +0xfc 0x40 0x1b 0x90 + +# CHECK: frip. 2, 3 +0xfc 0x40 0x1b 0x91 + +# CHECK: friz 2, 3 +0xfc 0x40 0x1b 0x50 + +# CHECK: friz. 2, 3 +0xfc 0x40 0x1b 0x51 + +# CHECK: frim 2, 3 +0xfc 0x40 0x1b 0xd0 + +# CHECK: frim. 2, 3 +0xfc 0x40 0x1b 0xd1 + +# CHECK: fcmpu 2, 3, 4 +0xfd 0x03 0x20 0x00 + +# CHECK: fsel 2, 3, 4, 5 +0xfc 0x43 0x29 0x2e + +# CHECK: fsel. 2, 3, 4, 5 +0xfc 0x43 0x29 0x2f + +# CHECK: mffs 2 +0xfc 0x40 0x04 0x8e + +# CHECK: mtfsb0 31 +0xff 0xe0 0x00 0x8c + +# CHECK: mtfsb1 31 +0xff 0xe0 0x00 0x4c + diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt new file mode 100644 index 00000000000..3896bf75543 --- /dev/null +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -0,0 +1,509 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s + +# CHECK: lvebx 2, 3, 4 +0x7c 0x43 0x20 0x0e + +# CHECK: lvehx 2, 3, 4 +0x7c 0x43 0x20 0x4e + +# CHECK: lvewx 2, 3, 4 +0x7c 0x43 0x20 0x8e + +# CHECK: lvx 2, 3, 4 +0x7c 0x43 0x20 0xce + +# CHECK: lvxl 2, 3, 4 +0x7c 0x43 0x22 0xce + +# CHECK: stvebx 2, 3, 4 +0x7c 0x43 0x21 0x0e + +# CHECK: stvehx 2, 3, 4 +0x7c 0x43 0x21 0x4e + +# CHECK: stvewx 2, 3, 4 +0x7c 0x43 0x21 0x8e + +# CHECK: stvx 2, 3, 4 +0x7c 0x43 0x21 0xce + +# CHECK: stvxl 2, 3, 4 +0x7c 0x43 0x23 0xce + +# CHECK: lvsl 2, 3, 4 +0x7c 0x43 0x20 0x0c + +# CHECK: lvsr 2, 3, 4 +0x7c 0x43 0x20 0x4c + +# CHECK: vpkpx 2, 3, 4 +0x10 0x43 0x23 0x0e + +# CHECK: vpkshss 2, 3, 4 +0x10 0x43 0x21 0x8e + +# CHECK: vpkshus 2, 3, 4 +0x10 0x43 0x21 0x0e + +# CHECK: vpkswss 2, 3, 4 +0x10 0x43 0x21 0xce + +# CHECK: vpkswus 2, 3, 4 +0x10 0x43 0x21 0x4e + +# CHECK: vpkuhum 2, 3, 4 +0x10 0x43 0x20 0x0e + +# CHECK: vpkuhus 2, 3, 4 +0x10 0x43 0x20 0x8e + +# CHECK: vpkuwum 2, 3, 4 +0x10 0x43 0x20 0x4e + +# CHECK: vpkuwus 2, 3, 4 +0x10 0x43 0x20 0xce + +# CHECK: vupkhpx 2, 3 +0x10 0x40 0x1b 0x4e + +# CHECK: vupkhsb 2, 3 +0x10 0x40 0x1a 0x0e + +# CHECK: vupkhsh 2, 3 +0x10 0x40 0x1a 0x4e + +# CHECK: vupklpx 2, 3 +0x10 0x40 0x1b 0xce + +# CHECK: vupklsb 2, 3 +0x10 0x40 0x1a 0x8e + +# CHECK: vupklsh 2, 3 +0x10 0x40 0x1a 0xce + +# CHECK: vmrghb 2, 3, 4 +0x10 0x43 0x20 0x0c + +# CHECK: vmrghh 2, 3, 4 +0x10 0x43 0x20 0x4c + +# CHECK: vmrghw 2, 3, 4 +0x10 0x43 0x20 0x8c + +# CHECK: vmrglb 2, 3, 4 +0x10 0x43 0x21 0x0c + +# CHECK: vmrglh 2, 3, 4 +0x10 0x43 0x21 0x4c + +# CHECK: vmrglw 2, 3, 4 +0x10 0x43 0x21 0x8c + +# CHECK: vspltb 2, 3, 1 +0x10 0x41 0x1a 0x0c + +# CHECK: vsplth 2, 3, 1 +0x10 0x41 0x1a 0x4c + +# CHECK: vspltw 2, 3, 1 +0x10 0x41 0x1a 0x8c + +# CHECK: vspltisb 2, 3 +0x10 0x43 0x03 0x0c + +# CHECK: vspltish 2, 3 +0x10 0x43 0x03 0x4c + +# CHECK: vspltisw 2, 3 +0x10 0x43 0x03 0x8c + +# CHECK: vperm 2, 3, 4, 5 +0x10 0x43 0x21 0x6b + +# CHECK: vsel 2, 3, 4, 5 +0x10 0x43 0x21 0x6a + +# CHECK: vsl 2, 3, 4 +0x10 0x43 0x21 0xc4 + +# CHECK: vsldoi 2, 3, 4, 5 +0x10 0x43 0x21 0x6c + +# CHECK: vslo 2, 3, 4 +0x10 0x43 0x24 0x0c + +# CHECK: vsr 2, 3, 4 +0x10 0x43 0x22 0xc4 + +# CHECK: vsro 2, 3, 4 +0x10 0x43 0x24 0x4c + +# CHECK: vaddcuw 2, 3, 4 +0x10 0x43 0x21 0x80 + +# CHECK: vaddsbs 2, 3, 4 +0x10 0x43 0x23 0x00 + +# CHECK: vaddshs 2, 3, 4 +0x10 0x43 0x23 0x40 + +# CHECK: vaddsws 2, 3, 4 +0x10 0x43 0x23 0x80 + +# CHECK: vaddubm 2, 3, 4 +0x10 0x43 0x20 0x00 + +# CHECK: vadduhm 2, 3, 4 +0x10 0x43 0x20 0x40 + +# CHECK: vadduwm 2, 3, 4 +0x10 0x43 0x20 0x80 + +# CHECK: vaddubs 2, 3, 4 +0x10 0x43 0x22 0x00 + +# CHECK: vadduhs 2, 3, 4 +0x10 0x43 0x22 0x40 + +# CHECK: vadduws 2, 3, 4 +0x10 0x43 0x22 0x80 + +# CHECK: vsubcuw 2, 3, 4 +0x10 0x43 0x25 0x80 + +# CHECK: vsubsbs 2, 3, 4 +0x10 0x43 0x27 0x00 + +# CHECK: vsubshs 2, 3, 4 +0x10 0x43 0x27 0x40 + +# CHECK: vsubsws 2, 3, 4 +0x10 0x43 0x27 0x80 + +# CHECK: vsububm 2, 3, 4 +0x10 0x43 0x24 0x00 + +# CHECK: vsubuhm 2, 3, 4 +0x10 0x43 0x24 0x40 + +# CHECK: vsubuwm 2, 3, 4 +0x10 0x43 0x24 0x80 + +# CHECK: vsububs 2, 3, 4 +0x10 0x43 0x26 0x00 + +# CHECK: vsubuhs 2, 3, 4 +0x10 0x43 0x26 0x40 + +# CHECK: vsubuws 2, 3, 4 +0x10 0x43 0x26 0x80 + +# CHECK: vmulesb 2, 3, 4 +0x10 0x43 0x23 0x08 + +# CHECK: vmulesh 2, 3, 4 +0x10 0x43 0x23 0x48 + +# CHECK: vmuleub 2, 3, 4 +0x10 0x43 0x22 0x08 + +# CHECK: vmuleuh 2, 3, 4 +0x10 0x43 0x22 0x48 + +# CHECK: vmulosb 2, 3, 4 +0x10 0x43 0x21 0x08 + +# CHECK: vmulosh 2, 3, 4 +0x10 0x43 0x21 0x48 + +# CHECK: vmuloub 2, 3, 4 +0x10 0x43 0x20 0x08 + +# CHECK: vmulouh 2, 3, 4 +0x10 0x43 0x20 0x48 + +# CHECK: vmhaddshs 2, 3, 4, 5 +0x10 0x43 0x21 0x60 + +# CHECK: vmhraddshs 2, 3, 4, 5 +0x10 0x43 0x21 0x61 + +# CHECK: vmladduhm 2, 3, 4, 5 +0x10 0x43 0x21 0x62 + +# CHECK: vmsumubm 2, 3, 4, 5 +0x10 0x43 0x21 0x64 + +# CHECK: vmsummbm 2, 3, 4, 5 +0x10 0x43 0x21 0x65 + +# CHECK: vmsumshm 2, 3, 4, 5 +0x10 0x43 0x21 0x68 + +# CHECK: vmsumshs 2, 3, 4, 5 +0x10 0x43 0x21 0x69 + +# CHECK: vmsumuhm 2, 3, 4, 5 +0x10 0x43 0x21 0x66 + +# CHECK: vmsumuhs 2, 3, 4, 5 +0x10 0x43 0x21 0x67 + +# CHECK: vsumsws 2, 3, 4 +0x10 0x43 0x27 0x88 + +# CHECK: vsum2sws 2, 3, 4 +0x10 0x43 0x26 0x88 + +# CHECK: vsum4sbs 2, 3, 4 +0x10 0x43 0x27 0x08 + +# CHECK: vsum4shs 2, 3, 4 +0x10 0x43 0x26 0x48 + +# CHECK: vsum4ubs 2, 3, 4 +0x10 0x43 0x26 0x08 + +# CHECK: vavgsb 2, 3, 4 +0x10 0x43 0x25 0x02 + +# CHECK: vavgsh 2, 3, 4 +0x10 0x43 0x25 0x42 + +# CHECK: vavgsw 2, 3, 4 +0x10 0x43 0x25 0x82 + +# CHECK: vavgub 2, 3, 4 +0x10 0x43 0x24 0x02 + +# CHECK: vavguh 2, 3, 4 +0x10 0x43 0x24 0x42 + +# CHECK: vavguw 2, 3, 4 +0x10 0x43 0x24 0x82 + +# CHECK: vmaxsb 2, 3, 4 +0x10 0x43 0x21 0x02 + +# CHECK: vmaxsh 2, 3, 4 +0x10 0x43 0x21 0x42 + +# CHECK: vmaxsw 2, 3, 4 +0x10 0x43 0x21 0x82 + +# CHECK: vmaxub 2, 3, 4 +0x10 0x43 0x20 0x02 + +# CHECK: vmaxuh 2, 3, 4 +0x10 0x43 0x20 0x42 + +# CHECK: vmaxuw 2, 3, 4 +0x10 0x43 0x20 0x82 + +# CHECK: vminsb 2, 3, 4 +0x10 0x43 0x23 0x02 + +# CHECK: vminsh 2, 3, 4 +0x10 0x43 0x23 0x42 + +# CHECK: vminsw 2, 3, 4 +0x10 0x43 0x23 0x82 + +# CHECK: vminub 2, 3, 4 +0x10 0x43 0x22 0x02 + +# CHECK: vminuh 2, 3, 4 +0x10 0x43 0x22 0x42 + +# CHECK: vminuw 2, 3, 4 +0x10 0x43 0x22 0x82 + +# CHECK: vcmpequb 2, 3, 4 +0x10 0x43 0x20 0x06 + +# CHECK: vcmpequb. 2, 3, 4 +0x10 0x43 0x24 0x06 + +# CHECK: vcmpequh 2, 3, 4 +0x10 0x43 0x20 0x46 + +# CHECK: vcmpequh. 2, 3, 4 +0x10 0x43 0x24 0x46 + +# CHECK: vcmpequw 2, 3, 4 +0x10 0x43 0x20 0x86 + +# CHECK: vcmpequw. 2, 3, 4 +0x10 0x43 0x24 0x86 + +# CHECK: vcmpgtsb 2, 3, 4 +0x10 0x43 0x23 0x06 + +# CHECK: vcmpgtsb. 2, 3, 4 +0x10 0x43 0x27 0x06 + +# CHECK: vcmpgtsh 2, 3, 4 +0x10 0x43 0x23 0x46 + +# CHECK: vcmpgtsh. 2, 3, 4 +0x10 0x43 0x27 0x46 + +# CHECK: vcmpgtsw 2, 3, 4 +0x10 0x43 0x23 0x86 + +# CHECK: vcmpgtsw. 2, 3, 4 +0x10 0x43 0x27 0x86 + +# CHECK: vcmpgtub 2, 3, 4 +0x10 0x43 0x22 0x06 + +# CHECK: vcmpgtub. 2, 3, 4 +0x10 0x43 0x26 0x06 + +# CHECK: vcmpgtuh 2, 3, 4 +0x10 0x43 0x22 0x46 + +# CHECK: vcmpgtuh. 2, 3, 4 +0x10 0x43 0x26 0x46 + +# CHECK: vcmpgtuw 2, 3, 4 +0x10 0x43 0x22 0x86 + +# CHECK: vcmpgtuw. 2, 3, 4 +0x10 0x43 0x26 0x86 + +# CHECK: vand 2, 3, 4 +0x10 0x43 0x24 0x04 + +# CHECK: vandc 2, 3, 4 +0x10 0x43 0x24 0x44 + +# CHECK: vnor 2, 3, 4 +0x10 0x43 0x25 0x04 + +# CHECK: vor 2, 3, 4 +0x10 0x43 0x24 0x84 + +# CHECK: vxor 2, 3, 4 +0x10 0x43 0x24 0xc4 + +# CHECK: vrlb 2, 3, 4 +0x10 0x43 0x20 0x04 + +# CHECK: vrlh 2, 3, 4 +0x10 0x43 0x20 0x44 + +# CHECK: vrlw 2, 3, 4 +0x10 0x43 0x20 0x84 + +# CHECK: vslb 2, 3, 4 +0x10 0x43 0x21 0x04 + +# CHECK: vslh 2, 3, 4 +0x10 0x43 0x21 0x44 + +# CHECK: vslw 2, 3, 4 +0x10 0x43 0x21 0x84 + +# CHECK: vsrb 2, 3, 4 +0x10 0x43 0x22 0x04 + +# CHECK: vsrh 2, 3, 4 +0x10 0x43 0x22 0x44 + +# CHECK: vsrw 2, 3, 4 +0x10 0x43 0x22 0x84 + +# CHECK: vsrab 2, 3, 4 +0x10 0x43 0x23 0x04 + +# CHECK: vsrah 2, 3, 4 +0x10 0x43 0x23 0x44 + +# CHECK: vsraw 2, 3, 4 +0x10 0x43 0x23 0x84 + +# CHECK: vaddfp 2, 3, 4 +0x10 0x43 0x20 0x0a + +# CHECK: vsubfp 2, 3, 4 +0x10 0x43 0x20 0x4a + +# CHECK: vmaddfp 2, 3, 4, 5 +0x10 0x43 0x29 0x2e + +# CHECK: vnmsubfp 2, 3, 4, 5 +0x10 0x43 0x29 0x2f + +# CHECK: vmaxfp 2, 3, 4 +0x10 0x43 0x24 0x0a + +# CHECK: vminfp 2, 3, 4 +0x10 0x43 0x24 0x4a + +# CHECK: vctsxs 2, 3, 4 +0x10 0x44 0x1b 0xca + +# CHECK: vctuxs 2, 3, 4 +0x10 0x44 0x1b 0x8a + +# CHECK: vcfsx 2, 3, 4 +0x10 0x44 0x1b 0x4a + +# CHECK: vcfux 2, 3, 4 +0x10 0x44 0x1b 0x0a + +# CHECK: vrfim 2, 3 +0x10 0x40 0x1a 0xca + +# CHECK: vrfin 2, 3 +0x10 0x40 0x1a 0x0a + +# CHECK: vrfip 2, 3 +0x10 0x40 0x1a 0x8a + +# CHECK: vrfiz 2, 3 +0x10 0x40 0x1a 0x4a + +# CHECK: vcmpbfp 2, 3, 4 +0x10 0x43 0x23 0xc6 + +# CHECK: vcmpbfp. 2, 3, 4 +0x10 0x43 0x27 0xc6 + +# CHECK: vcmpeqfp 2, 3, 4 +0x10 0x43 0x20 0xc6 + +# CHECK: vcmpeqfp. 2, 3, 4 +0x10 0x43 0x24 0xc6 + +# CHECK: vcmpgefp 2, 3, 4 +0x10 0x43 0x21 0xc6 + +# CHECK: vcmpgefp. 2, 3, 4 +0x10 0x43 0x25 0xc6 + +# CHECK: vcmpgtfp 2, 3, 4 +0x10 0x43 0x22 0xc6 + +# CHECK: vcmpgtfp. 2, 3, 4 +0x10 0x43 0x26 0xc6 + +# CHECK: vexptefp 2, 3 +0x10 0x40 0x19 0x8a + +# CHECK: vlogefp 2, 3 +0x10 0x40 0x19 0xca + +# CHECK: vrefp 2, 3 +0x10 0x40 0x19 0x0a + +# CHECK: vrsqrtefp 2, 3 +0x10 0x40 0x19 0x4a + +# CHECK: mtvscr 2 +0x10 0x00 0x16 0x44 + +# CHECK: mfvscr 2 +0x10 0x40 0x06 0x04 + diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt new file mode 100644 index 00000000000..33a8c0ed5de --- /dev/null +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt @@ -0,0 +1,621 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s + +# FIXME: test b target + +# FIXME: test ba target + +# FIXME: test bl target + +# FIXME: test bla target + +# FIXME: test bc 4, 10, target + +# FIXME: test bca 4, 10, target + +# FIXME: test bcl 4, 10, target + +# FIXME: test bcla 4, 10, target + +# CHECK: bclr 4, 10, 3 +0x4c 0x8a 0x18 0x20 + +# CHECK: bclr 4, 10, 0 +0x4c 0x8a 0x00 0x20 + +# CHECK: bclrl 4, 10, 3 +0x4c 0x8a 0x18 0x21 + +# CHECK: bclrl 4, 10, 0 +0x4c 0x8a 0x00 0x21 + +# CHECK: bcctr 4, 10, 3 +0x4c 0x8a 0x1c 0x20 + +# CHECK: bcctr 4, 10, 0 +0x4c 0x8a 0x04 0x20 + +# CHECK: bcctrl 4, 10, 3 +0x4c 0x8a 0x1c 0x21 + +# CHECK: bcctrl 4, 10, 0 +0x4c 0x8a 0x04 0x21 + +# CHECK: crand 2, 3, 4 +0x4c 0x43 0x22 0x02 + +# CHECK: crnand 2, 3, 4 +0x4c 0x43 0x21 0xc2 + +# CHECK: cror 2, 3, 4 +0x4c 0x43 0x23 0x82 + +# CHECK: crxor 2, 3, 4 +0x4c 0x43 0x21 0x82 + +# CHECK: crnor 2, 3, 4 +0x4c 0x43 0x20 0x42 + +# CHECK: creqv 2, 3, 4 +0x4c 0x43 0x22 0x42 + +# CHECK: crandc 2, 3, 4 +0x4c 0x43 0x21 0x02 + +# CHECK: crorc 2, 3, 4 +0x4c 0x43 0x23 0x42 + +# CHECK: mcrf 2, 3 +0x4d 0x0c 0x00 0x00 + +# CHECK: sc 1 +0x44 0x00 0x00 0x22 + +# CHECK: sc 0 +0x44 0x00 0x00 0x02 + +# CHECK: lbz 2, 128(4) +0x88 0x44 0x00 0x80 + +# CHECK: lbzx 2, 3, 4 +0x7c 0x43 0x20 0xae + +# CHECK: lbzu 2, 128(4) +0x8c 0x44 0x00 0x80 + +# CHECK: lbzux 2, 3, 4 +0x7c 0x43 0x20 0xee + +# CHECK: lhz 2, 128(4) +0xa0 0x44 0x00 0x80 + +# CHECK: lhzx 2, 3, 4 +0x7c 0x43 0x22 0x2e + +# CHECK: lhzu 2, 128(4) +0xa4 0x44 0x00 0x80 + +# CHECK: lhzux 2, 3, 4 +0x7c 0x43 0x22 0x6e + +# CHECK: lha 2, 128(4) +0xa8 0x44 0x00 0x80 + +# CHECK: lhax 2, 3, 4 +0x7c 0x43 0x22 0xae + +# CHECK: lhau 2, 128(4) +0xac 0x44 0x00 0x80 + +# CHECK: lhaux 2, 3, 4 +0x7c 0x43 0x22 0xee + +# CHECK: lwz 2, 128(4) +0x80 0x44 0x00 0x80 + +# CHECK: lwzx 2, 3, 4 +0x7c 0x43 0x20 0x2e + +# CHECK: lwzu 2, 128(4) +0x84 0x44 0x00 0x80 + +# CHECK: lwzux 2, 3, 4 +0x7c 0x43 0x20 0x6e + +# CHECK: lwa 2, 128(4) +0xe8 0x44 0x00 0x82 + +# CHECK: lwax 2, 3, 4 +0x7c 0x43 0x22 0xaa + +# CHECK: lwaux 2, 3, 4 +0x7c 0x43 0x22 0xea + +# CHECK: ld 2, 128(4) +0xe8 0x44 0x00 0x80 + +# CHECK: ldx 2, 3, 4 +0x7c 0x43 0x20 0x2a + +# CHECK: ldu 2, 128(4) +0xe8 0x44 0x00 0x81 + +# CHECK: ldux 2, 3, 4 +0x7c 0x43 0x20 0x6a + +# CHECK: stb 2, 128(4) +0x98 0x44 0x00 0x80 + +# CHECK: stbx 2, 3, 4 +0x7c 0x43 0x21 0xae + +# CHECK: stbu 2, 128(4) +0x9c 0x44 0x00 0x80 + +# CHECK: stbux 2, 3, 4 +0x7c 0x43 0x21 0xee + +# CHECK: sth 2, 128(4) +0xb0 0x44 0x00 0x80 + +# CHECK: sthx 2, 3, 4 +0x7c 0x43 0x23 0x2e + +# CHECK: sthu 2, 128(4) +0xb4 0x44 0x00 0x80 + +# CHECK: sthux 2, 3, 4 +0x7c 0x43 0x23 0x6e + +# CHECK: stw 2, 128(4) +0x90 0x44 0x00 0x80 + +# CHECK: stwx 2, 3, 4 +0x7c 0x43 0x21 0x2e + +# CHECK: stwu 2, 128(4) +0x94 0x44 0x00 0x80 + +# CHECK: stwux 2, 3, 4 +0x7c 0x43 0x21 0x6e + +# CHECK: std 2, 128(4) +0xf8 0x44 0x00 0x80 + +# CHECK: stdx 2, 3, 4 +0x7c 0x43 0x21 0x2a + +# CHECK: stdu 2, 128(4) +0xf8 0x44 0x00 0x81 + +# CHECK: stdux 2, 3, 4 +0x7c 0x43 0x21 0x6a + +# CHECK: lhbrx 2, 3, 4 +0x7c 0x43 0x26 0x2c + +# CHECK: sthbrx 2, 3, 4 +0x7c 0x43 0x27 0x2c + +# CHECK: lwbrx 2, 3, 4 +0x7c 0x43 0x24 0x2c + +# CHECK: stwbrx 2, 3, 4 +0x7c 0x43 0x25 0x2c + +# CHECK: ldbrx 2, 3, 4 +0x7c 0x43 0x24 0x28 + +# CHECK: stdbrx 2, 3, 4 +0x7c 0x43 0x25 0x28 + +# CHECK: lmw 2, 128(1) +0xb8 0x41 0x00 0x80 + +# CHECK: stmw 2, 128(1) +0xbc 0x41 0x00 0x80 + +# CHECK: addi 2, 3, 128 +0x38 0x43 0x00 0x80 + +# CHECK: addis 2, 3, 128 +0x3c 0x43 0x00 0x80 + +# CHECK: add 2, 3, 4 +0x7c 0x43 0x22 0x14 + +# CHECK: add. 2, 3, 4 +0x7c 0x43 0x22 0x15 + +# CHECK: subf 2, 3, 4 +0x7c 0x43 0x20 0x50 + +# CHECK: subf. 2, 3, 4 +0x7c 0x43 0x20 0x51 + +# CHECK: addic 2, 3, 128 +0x30 0x43 0x00 0x80 + +# CHECK: addic. 2, 3, 128 +0x34 0x43 0x00 0x80 + +# CHECK: subfic 2, 3, 4 +0x20 0x43 0x00 0x04 + +# CHECK: addc 2, 3, 4 +0x7c 0x43 0x20 0x14 + +# CHECK: addc. 2, 3, 4 +0x7c 0x43 0x20 0x15 + +# CHECK: subfc 2, 3, 4 +0x7c 0x43 0x20 0x10 + +# CHECK: subfc 2, 3, 4 +0x7c 0x43 0x20 0x10 + +# CHECK: adde 2, 3, 4 +0x7c 0x43 0x21 0x14 + +# CHECK: adde. 2, 3, 4 +0x7c 0x43 0x21 0x15 + +# CHECK: subfe 2, 3, 4 +0x7c 0x43 0x21 0x10 + +# CHECK: subfe. 2, 3, 4 +0x7c 0x43 0x21 0x11 + +# CHECK: addme 2, 3 +0x7c 0x43 0x01 0xd4 + +# CHECK: addme. 2, 3 +0x7c 0x43 0x01 0xd5 + +# CHECK: subfme 2, 3 +0x7c 0x43 0x01 0xd0 + +# CHECK: subfme. 2, 3 +0x7c 0x43 0x01 0xd1 + +# CHECK: addze 2, 3 +0x7c 0x43 0x01 0x94 + +# CHECK: addze. 2, 3 +0x7c 0x43 0x01 0x95 + +# CHECK: subfze 2, 3 +0x7c 0x43 0x01 0x90 + +# CHECK: subfze. 2, 3 +0x7c 0x43 0x01 0x91 + +# CHECK: neg 2, 3 +0x7c 0x43 0x00 0xd0 + +# CHECK: neg. 2, 3 +0x7c 0x43 0x00 0xd1 + +# CHECK: mulli 2, 3, 128 +0x1c 0x43 0x00 0x80 + +# CHECK: mulhw 2, 3, 4 +0x7c 0x43 0x20 0x96 + +# CHECK: mulhw. 2, 3, 4 +0x7c 0x43 0x20 0x97 + +# CHECK: mullw 2, 3, 4 +0x7c 0x43 0x21 0xd6 + +# CHECK: mullw. 2, 3, 4 +0x7c 0x43 0x21 0xd7 + +# CHECK: mulhwu 2, 3, 4 +0x7c 0x43 0x20 0x16 + +# CHECK: mulhwu. 2, 3, 4 +0x7c 0x43 0x20 0x17 + +# CHECK: divw 2, 3, 4 +0x7c 0x43 0x23 0xd6 + +# CHECK: divw. 2, 3, 4 +0x7c 0x43 0x23 0xd7 + +# CHECK: divwu 2, 3, 4 +0x7c 0x43 0x23 0x96 + +# CHECK: divwu. 2, 3, 4 +0x7c 0x43 0x23 0x97 + +# CHECK: mulld 2, 3, 4 +0x7c 0x43 0x21 0xd2 + +# CHECK: mulld. 2, 3, 4 +0x7c 0x43 0x21 0xd3 + +# CHECK: mulhd 2, 3, 4 +0x7c 0x43 0x20 0x92 + +# CHECK: mulhd. 2, 3, 4 +0x7c 0x43 0x20 0x93 + +# CHECK: mulhdu 2, 3, 4 +0x7c 0x43 0x20 0x12 + +# CHECK: mulhdu. 2, 3, 4 +0x7c 0x43 0x20 0x13 + +# CHECK: divd 2, 3, 4 +0x7c 0x43 0x23 0xd2 + +# CHECK: divd. 2, 3, 4 +0x7c 0x43 0x23 0xd3 + +# CHECK: divdu 2, 3, 4 +0x7c 0x43 0x23 0x92 + +# CHECK: divdu. 2, 3, 4 +0x7c 0x43 0x23 0x93 + +# CHECK: cmpdi 2, 3, 128 +0x2d 0x23 0x00 0x80 + +# CHECK: cmpd 2, 3, 4 +0x7d 0x23 0x20 0x00 + +# CHECK: cmpldi 2, 3, 128 +0x29 0x23 0x00 0x80 + +# CHECK: cmpld 2, 3, 4 +0x7d 0x23 0x20 0x40 + +# CHECK: cmpwi 2, 3, 128 +0x2d 0x03 0x00 0x80 + +# CHECK: cmpw 2, 3, 4 +0x7d 0x03 0x20 0x00 + +# CHECK: cmplwi 2, 3, 128 +0x29 0x03 0x00 0x80 + +# CHECK: cmplw 2, 3, 4 +0x7d 0x03 0x20 0x40 + +# CHECK: twi 2, 3, 4 +0x0c 0x43 0x00 0x04 + +# CHECK: tw 2, 3, 4 +0x7c 0x43 0x20 0x08 + +# CHECK: tdi 2, 3, 4 +0x08 0x43 0x00 0x04 + +# CHECK: td 2, 3, 4 +0x7c 0x43 0x20 0x88 + +# CHECK: isel 2, 3, 4, 5 +0x7c 0x43 0x21 0x5e + +# CHECK: andi. 2, 3, 128 +0x70 0x62 0x00 0x80 + +# CHECK: andis. 2, 3, 128 +0x74 0x62 0x00 0x80 + +# CHECK: ori 2, 3, 128 +0x60 0x62 0x00 0x80 + +# CHECK: oris 2, 3, 128 +0x64 0x62 0x00 0x80 + +# CHECK: xori 2, 3, 128 +0x68 0x62 0x00 0x80 + +# CHECK: xoris 2, 3, 128 +0x6c 0x62 0x00 0x80 + +# CHECK: and 2, 3, 4 +0x7c 0x62 0x20 0x38 + +# CHECK: and. 2, 3, 4 +0x7c 0x62 0x20 0x39 + +# CHECK: xor 2, 3, 4 +0x7c 0x62 0x22 0x78 + +# CHECK: xor. 2, 3, 4 +0x7c 0x62 0x22 0x79 + +# CHECK: nand 2, 3, 4 +0x7c 0x62 0x23 0xb8 + +# CHECK: nand. 2, 3, 4 +0x7c 0x62 0x23 0xb9 + +# CHECK: or 2, 3, 4 +0x7c 0x62 0x23 0x78 + +# CHECK: or. 2, 3, 4 +0x7c 0x62 0x23 0x79 + +# CHECK: nor 2, 3, 4 +0x7c 0x62 0x20 0xf8 + +# CHECK: nor. 2, 3, 4 +0x7c 0x62 0x20 0xf9 + +# CHECK: eqv 2, 3, 4 +0x7c 0x62 0x22 0x38 + +# CHECK: eqv. 2, 3, 4 +0x7c 0x62 0x22 0x39 + +# CHECK: andc 2, 3, 4 +0x7c 0x62 0x20 0x78 + +# CHECK: andc. 2, 3, 4 +0x7c 0x62 0x20 0x79 + +# CHECK: orc 2, 3, 4 +0x7c 0x62 0x23 0x38 + +# CHECK: orc. 2, 3, 4 +0x7c 0x62 0x23 0x39 + +# CHECK: extsb 2, 3 +0x7c 0x62 0x07 0x74 + +# CHECK: extsb. 2, 3 +0x7c 0x62 0x07 0x75 + +# CHECK: extsh 2, 3 +0x7c 0x62 0x07 0x34 + +# CHECK: extsh. 2, 3 +0x7c 0x62 0x07 0x35 + +# CHECK: cntlzw 2, 3 +0x7c 0x62 0x00 0x34 + +# CHECK: cntlzw. 2, 3 +0x7c 0x62 0x00 0x35 + +# CHECK: popcntw 2, 3 +0x7c 0x62 0x02 0xf4 + +# CHECK: extsw 2, 3 +0x7c 0x62 0x07 0xb4 + +# CHECK: extsw. 2, 3 +0x7c 0x62 0x07 0xb5 + +# CHECK: cntlzd 2, 3 +0x7c 0x62 0x00 0x74 + +# CHECK: cntlzd. 2, 3 +0x7c 0x62 0x00 0x75 + +# CHECK: popcntd 2, 3 +0x7c 0x62 0x03 0xf4 + +# CHECK: rlwinm 2, 3, 4, 5, 6 +0x54 0x62 0x21 0x4c + +# CHECK: rlwinm. 2, 3, 4, 5, 6 +0x54 0x62 0x21 0x4d + +# CHECK: rlwnm 2, 3, 4, 5, 6 +0x5c 0x62 0x21 0x4c + +# CHECK: rlwnm. 2, 3, 4, 5, 6 +0x5c 0x62 0x21 0x4d + +# CHECK: rlwimi 2, 3, 4, 5, 6 +0x50 0x62 0x21 0x4c + +# CHECK: rlwimi. 2, 3, 4, 5, 6 +0x50 0x62 0x21 0x4d + +# CHECK: rldicl 2, 3, 4, 5 +0x78 0x62 0x21 0x40 + +# CHECK: rldicl. 2, 3, 4, 5 +0x78 0x62 0x21 0x41 + +# CHECK: rldicr 2, 3, 4, 5 +0x78 0x62 0x21 0x44 + +# CHECK: rldicr. 2, 3, 4, 5 +0x78 0x62 0x21 0x45 + +# CHECK: rldic 2, 3, 4, 5 +0x78 0x62 0x21 0x48 + +# CHECK: rldic. 2, 3, 4, 5 +0x78 0x62 0x21 0x49 + +# CHECK: rldcl 2, 3, 4, 5 +0x78 0x62 0x21 0x50 + +# CHECK: rldcl. 2, 3, 4, 5 +0x78 0x62 0x21 0x51 + +# CHECK: rldcr 2, 3, 4, 5 +0x78 0x62 0x21 0x52 + +# CHECK: rldcr. 2, 3, 4, 5 +0x78 0x62 0x21 0x53 + +# CHECK: rldimi 2, 3, 4, 5 +0x78 0x62 0x21 0x4c + +# CHECK: rldimi. 2, 3, 4, 5 +0x78 0x62 0x21 0x4d + +# CHECK: slw 2, 3, 4 +0x7c 0x62 0x20 0x30 + +# CHECK: slw. 2, 3, 4 +0x7c 0x62 0x20 0x31 + +# CHECK: srw 2, 3, 4 +0x7c 0x62 0x24 0x30 + +# CHECK: srw. 2, 3, 4 +0x7c 0x62 0x24 0x31 + +# CHECK: srawi 2, 3, 4 +0x7c 0x62 0x26 0x70 + +# CHECK: srawi. 2, 3, 4 +0x7c 0x62 0x26 0x71 + +# CHECK: sraw 2, 3, 4 +0x7c 0x62 0x26 0x30 + +# CHECK: sraw. 2, 3, 4 +0x7c 0x62 0x26 0x31 + +# CHECK: sld 2, 3, 4 +0x7c 0x62 0x20 0x36 + +# CHECK: sld. 2, 3, 4 +0x7c 0x62 0x20 0x37 + +# CHECK: srd 2, 3, 4 +0x7c 0x62 0x24 0x36 + +# CHECK: srd. 2, 3, 4 +0x7c 0x62 0x24 0x37 + +# CHECK: sradi 2, 3, 4 +0x7c 0x62 0x26 0x74 + +# CHECK: sradi. 2, 3, 4 +0x7c 0x62 0x26 0x75 + +# CHECK: srad 2, 3, 4 +0x7c 0x62 0x26 0x34 + +# CHECK: srad. 2, 3, 4 +0x7c 0x62 0x26 0x35 + +# CHECK: mtspr 600, 2 +0x7c 0x58 0x93 0xa6 + +# CHECK: mfspr 2, 600 +0x7c 0x58 0x92 0xa6 + +# CHECK: mtcrf 123, 2 +0x7c 0x47 0xb1 0x20 + +# CHECK: mfcr 2 +0x7c 0x40 0x00 0x26 + +# CHECK: mtocrf 16, 2 +0x7c 0x51 0x01 0x20 + +# CHECK: mfocrf 16, 8 +0x7e 0x10 0x80 0x26 + diff --git a/test/MC/Disassembler/PowerPC/ppc64-operands.txt b/test/MC/Disassembler/PowerPC/ppc64-operands.txt new file mode 100644 index 00000000000..a2da3227f7c --- /dev/null +++ b/test/MC/Disassembler/PowerPC/ppc64-operands.txt @@ -0,0 +1,94 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s + +# CHECK: add 1, 2, 3 +0x7c 0x22 0x1a 0x14 + +# CHECK: add 1, 2, 3 +0x7c 0x22 0x1a 0x14 + +# CHECK: add 0, 0, 0 +0x7c 0x00 0x02 0x14 + +# CHECK: add 31, 31, 31 +0x7f 0xff 0xfa 0x14 + +# CHECK: li 1, 0 +0x38 0x20 0x00 0x00 + +# CHECK: addi 1, 2, 0 +0x38 0x22 0x00 0x00 + +# CHECK: li 1, -32768 +0x38 0x20 0x80 0x00 + +# CHECK: li 1, 32767 +0x38 0x20 0x7f 0xff + +# CHECK: ori 1, 2, 0 +0x60 0x41 0x00 0x00 + +# CHECK: ori 1, 2, 65535 +0x60 0x41 0xff 0xff + +# CHECK: lis 1, 0 +0x3c 0x20 0x00 0x00 + +# CHECK: lis 1, -1 +0x3c 0x20 0xff 0xff + +# CHECK: lwz 1, 0(0) +0x80 0x20 0x00 0x00 + +# CHECK: lwz 1, 0(0) +0x80 0x20 0x00 0x00 + +# CHECK: lwz 1, 0(31) +0x80 0x3f 0x00 0x00 + +# CHECK: lwz 1, 0(31) +0x80 0x3f 0x00 0x00 + +# CHECK: lwz 1, -32768(2) +0x80 0x22 0x80 0x00 + +# CHECK: lwz 1, 32767(2) +0x80 0x22 0x7f 0xff + +# CHECK: ld 1, 0(0) +0xe8 0x20 0x00 0x00 + +# CHECK: ld 1, 0(0) +0xe8 0x20 0x00 0x00 + +# CHECK: ld 1, 0(31) +0xe8 0x3f 0x00 0x00 + +# CHECK: ld 1, 0(31) +0xe8 0x3f 0x00 0x00 + +# CHECK: ld 1, -32768(2) +0xe8 0x22 0x80 0x00 + +# CHECK: ld 1, 32764(2) +0xe8 0x22 0x7f 0xfc + +# CHECK: ld 1, 4(2) +0xe8 0x22 0x00 0x04 + +# CHECK: ld 1, -4(2) +0xe8 0x22 0xff 0xfc + +# CHECK: b .+1024 +0x48 0x00 0x04 0x00 + +# CHECK: ba 1024 +0x48 0x00 0x04 0x02 + +# FIXME: decode as beq 0, .+1024 +# CHECK: bc 12, 2, .+1024 +0x41 0x82 0x04 0x00 + +# FIXME: decode as beqa 0, 1024 +# CHECK: bca 12, 2, 1024 +0x41 0x82 0x04 0x02 +