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Add support to Legalize for expanding i64 sextload/zextload into hi and lo
parts. This should fix the crafty and signed long long unit test failure on x86 last night. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23711 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3101,6 +3101,41 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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Hi = LegalizeOp(Hi);
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Hi = LegalizeOp(Hi);
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break;
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break;
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}
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}
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case ISD::SEXTLOAD: {
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SDOperand Chain = LegalizeOp(Node->getOperand(0));
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SDOperand Ptr = LegalizeOp(Node->getOperand(1));
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MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
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if (EVT == NVT)
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Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
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else
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Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
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EVT);
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// The high part is obtained by SRA'ing all but one of the bits of the lo
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// part.
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unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
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Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
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TLI.getShiftAmountTy()));
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Lo = LegalizeOp(Lo);
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Hi = LegalizeOp(Hi);
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break;
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}
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case ISD::ZEXTLOAD: {
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SDOperand Chain = LegalizeOp(Node->getOperand(0));
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SDOperand Ptr = LegalizeOp(Node->getOperand(1));
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MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
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if (EVT == NVT)
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Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
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else
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
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EVT);
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// The high part is just a zero.
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Hi = DAG.getConstant(0, NVT);
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Lo = LegalizeOp(Lo);
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Hi = LegalizeOp(Hi);
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break;
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}
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case ISD::ANY_EXTEND: {
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case ISD::ANY_EXTEND: {
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SDOperand In;
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SDOperand In;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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