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https://github.com/RPCS3/llvm.git
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Fix pre- and post-indexed load / store encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59230 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
a6ce05f82a
commit
148cad8b30
@ -312,10 +312,12 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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case ARMII::DPSoRegFrm:
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emitDataProcessingInstruction(MI);
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break;
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case ARMII::LdStFrm:
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case ARMII::LdFrm:
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case ARMII::StFrm:
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emitLoadStoreInstruction(MI);
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break;
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case ARMII::LdStMiscFrm:
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case ARMII::LdMiscFrm:
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case ARMII::StMiscFrm:
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emitMiscLoadStoreInstruction(MI);
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break;
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case ARMII::LdStMulFrm:
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@ -687,6 +689,8 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRd,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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unsigned Form = TID.TSFlags & ARMII::FormMask;
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bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -694,8 +698,17 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Set first operand
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unsigned OpIdx = 0;
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// Operand 0 of a pre- and post-indexed store is the address base
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// writeback. Skip it.
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bool Skipped = false;
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if (IsPrePost && Form == ARMII::StFrm) {
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++OpIdx;
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Skipped = true;
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}
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// Set first operand
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if (ImplicitRd)
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
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@ -712,7 +725,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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// If this is a two-address operand, skip it. e.g. LDR_PRE.
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if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
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if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
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++OpIdx;
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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@ -749,6 +762,8 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRn) {
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const TargetInstrDesc &TID = MI.getDesc();
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unsigned Form = TID.TSFlags & ARMII::FormMask;
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bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -756,11 +771,20 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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unsigned OpIdx = 0;
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// Operand 0 of a pre- and post-indexed store is the address base
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// writeback. Skip it.
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bool Skipped = false;
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if (IsPrePost && Form == ARMII::StMiscFrm) {
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++OpIdx;
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Skipped = true;
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}
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
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// Set second operand
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unsigned OpIdx = 1;
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if (ImplicitRn)
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
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@ -769,7 +793,7 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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// If this is a two-address operand, skip it. e.g. LDRH_POST.
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if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
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if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
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++OpIdx;
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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@ -27,25 +27,27 @@ def BrMiscFrm : Format<4>;
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def DPFrm : Format<5>;
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def DPSoRegFrm : Format<6>;
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def LdStFrm : Format<7>;
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def LdStMiscFrm : Format<8>;
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def LdStMulFrm : Format<9>;
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def LdFrm : Format<7>;
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def StFrm : Format<8>;
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def LdMiscFrm : Format<9>;
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def StMiscFrm : Format<10>;
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def LdStMulFrm : Format<11>;
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def ArithMiscFrm : Format<10>;
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def ExtFrm : Format<11>;
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def ArithMiscFrm : Format<12>;
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def ExtFrm : Format<13>;
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def VFPUnaryFrm : Format<12>;
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def VFPBinaryFrm : Format<13>;
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def VFPConv1Frm : Format<14>;
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def VFPConv2Frm : Format<15>;
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def VFPConv3Frm : Format<16>;
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def VFPConv4Frm : Format<17>;
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def VFPConv5Frm : Format<18>;
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def VFPLdStFrm : Format<19>;
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def VFPLdStMulFrm : Format<20>;
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def VFPMiscFrm : Format<21>;
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def VFPUnaryFrm : Format<14>;
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def VFPBinaryFrm : Format<15>;
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def VFPConv1Frm : Format<16>;
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def VFPConv2Frm : Format<17>;
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def VFPConv3Frm : Format<18>;
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def VFPConv4Frm : Format<19>;
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def VFPConv5Frm : Format<20>;
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def VFPLdStFrm : Format<21>;
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def VFPLdStMulFrm : Format<22>;
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def VFPMiscFrm : Format<23>;
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def ThumbFrm : Format<22>;
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def ThumbFrm : Format<24>;
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// Misc flag for data processing instructions that indicates whether
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// the instruction has a Rn register operand.
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@ -87,30 +87,32 @@ namespace ARMII {
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DPSoRegFrm = 6 << FormShift,
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// Load and Store
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LdStFrm = 7 << FormShift,
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LdStMiscFrm = 8 << FormShift,
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LdStMulFrm = 9 << FormShift,
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LdFrm = 7 << FormShift,
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StFrm = 8 << FormShift,
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LdMiscFrm = 9 << FormShift,
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StMiscFrm = 10 << FormShift,
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LdStMulFrm = 11 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMiscFrm = 10 << FormShift,
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ArithMiscFrm = 12 << FormShift,
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// Extend instructions
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ExtFrm = 11 << FormShift,
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ExtFrm = 13 << FormShift,
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// VFP formats
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VFPUnaryFrm = 12 << FormShift,
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VFPBinaryFrm = 13 << FormShift,
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VFPConv1Frm = 14 << FormShift,
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VFPConv2Frm = 15 << FormShift,
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VFPConv3Frm = 16 << FormShift,
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VFPConv4Frm = 17 << FormShift,
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VFPConv5Frm = 18 << FormShift,
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VFPLdStFrm = 19 << FormShift,
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VFPLdStMulFrm = 20 << FormShift,
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VFPMiscFrm = 21 << FormShift,
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VFPUnaryFrm = 14 << FormShift,
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VFPBinaryFrm = 15 << FormShift,
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VFPConv1Frm = 16 << FormShift,
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VFPConv2Frm = 17 << FormShift,
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VFPConv3Frm = 18 << FormShift,
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VFPConv4Frm = 19 << FormShift,
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VFPConv5Frm = 20 << FormShift,
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VFPLdStFrm = 21 << FormShift,
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VFPLdStMulFrm = 22 << FormShift,
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VFPMiscFrm = 23 << FormShift,
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// Thumb format
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ThumbFrm = 22 << FormShift,
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ThumbFrm = 24 << FormShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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@ -615,134 +615,134 @@ let isBranch = 1, isTerminator = 1 in {
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// Load
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let isSimpleLoad = 1 in
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def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm,
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def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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"ldr", " $dst, $addr",
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[(set GPR:$dst, (load addrmode2:$addr))]>;
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// Special LDR for loads from non-pc-relative constpools.
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let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm,
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def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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"ldr", " $dst, $addr", []>;
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// Loads with zero extension
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def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm,
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def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
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"ldr", "h $dst, $addr",
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[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
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def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm,
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def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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"ldr", "b $dst, $addr",
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[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
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// Loads with sign extension
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def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm,
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def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
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"ldr", "sh $dst, $addr",
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[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
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def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm,
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def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
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"ldr", "sb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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let mayLoad = 1 in {
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// Load doubleword
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def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm,
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def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
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"ldr", "d $dst, $addr",
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[]>, Requires<[IsARM, HasV5T]>;
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// Indexed loads
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def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
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(ins addrmode2:$addr), LdStFrm,
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(ins addrmode2:$addr), LdFrm,
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"ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
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def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am2offset:$offset), LdStFrm,
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(ins GPR:$base, am2offset:$offset), LdFrm,
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"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
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def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
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(ins addrmode3:$addr), LdStMiscFrm,
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(ins addrmode3:$addr), LdMiscFrm,
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"ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
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def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am3offset:$offset), LdStMiscFrm,
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(ins GPR:$base,am3offset:$offset), LdMiscFrm,
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"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
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def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
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(ins addrmode2:$addr), LdStFrm,
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(ins addrmode2:$addr), LdFrm,
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"ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
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def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am2offset:$offset), LdStFrm,
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(ins GPR:$base,am2offset:$offset), LdFrm,
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"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
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def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
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(ins addrmode3:$addr), LdStMiscFrm,
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(ins addrmode3:$addr), LdMiscFrm,
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"ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
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def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am3offset:$offset), LdStMiscFrm,
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"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
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(ins GPR:$base,am3offset:$offset), LdMiscFrm,
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"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
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def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
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(ins addrmode3:$addr), LdStMiscFrm,
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(ins addrmode3:$addr), LdMiscFrm,
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"ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
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def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am3offset:$offset), LdStMiscFrm,
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(ins GPR:$base,am3offset:$offset), LdMiscFrm,
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"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
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}
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// Store
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def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm,
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def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
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"str", " $src, $addr",
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[(store GPR:$src, addrmode2:$addr)]>;
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// Stores with truncate
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def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm,
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def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
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"str", "h $src, $addr",
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[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
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def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm,
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def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
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"str", "b $src, $addr",
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[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
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// Store doubleword
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let mayStore = 1 in
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def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm,
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def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
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"str", "d $src, $addr",
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[]>, Requires<[IsARM, HasV5T]>;
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// Indexed stores
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def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base, am2offset:$offset), LdStFrm,
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(ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
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"str", " $src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb,
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(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
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def STR_POST : AI2stwpo<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm,
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(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
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"str", " $src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb,
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(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
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def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm,
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(ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
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"str", "h $src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb,
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(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
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def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm,
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(ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
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"str", "h $src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
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GPR:$base, am3offset:$offset))]>;
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def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm,
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(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
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"str", "b $src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
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GPR:$base, am2offset:$offset))]>;
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def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm,
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(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
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"str", "b $src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
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GPR:$base, am2offset:$offset))]>;
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