mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-28 23:43:50 +00:00
* Don't save LR when outputting globals: it's already saved on the stack once
for the function * Registers aren't necessarily sequential wrt their enums, don't rely on it when emitting function arguments into sequential registers * Remove X86-specific comments about AL/BL/AH/BH/EDX/etc * Add an abort() for an unimplemented signed right shift * The src operand for a GEP was never emitted! Fixed. * We can skip zero-valued GEP indices as they are no-ops. "Hello, World!" now works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
61297ee118
commit
14d8c7a6a0
@ -366,16 +366,11 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
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return Reg;
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} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
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// GV is located at PC + distance
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unsigned LRsave = makeAnotherReg(Type::IntTy);
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unsigned CurPC = makeAnotherReg(Type::IntTy);
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unsigned Reg1 = makeAnotherReg(V->getType());
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unsigned Reg2 = makeAnotherReg(V->getType());
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// Save the old LR
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BuildMI(*MBB, IPt, PPC32::MFLR, 0, LRsave);
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// Move PC to destination reg
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BuildMI(*MBB, IPt, PPC32::MovePCtoLR, 0, CurPC);
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// Restore the old LR
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BuildMI(*MBB, IPt, PPC32::MTLR, 1).addReg(LRsave);
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// Move value at PC + distance into return reg
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BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
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.addGlobalAddress(GV);
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@ -1202,10 +1197,16 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Arguments go on the stack in reverse order, as specified by the ABI.
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unsigned ArgOffset = 0;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned GPR_idx = 3;
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unsigned FPR_idx = 1;
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int GPR_remaining = 8, FPR_remaining = 8;
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unsigned GPR[] = {
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PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
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PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
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};
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unsigned FPR[] = {
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PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4,
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PPC32::F5, PPC32::F6, PPC32::F7, PPC32::F8
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};
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unsigned GPR_idx = 0, FPR_idx = 0;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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unsigned ArgReg;
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@ -1218,7 +1219,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Reg or stack?
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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} else {
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BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
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@ -1230,7 +1231,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Reg or stack?
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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} else {
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BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
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@ -1242,9 +1243,9 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Reg or stack?
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if (GPR_remaining > 1) {
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx + 1).addReg(ArgReg+1)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx + 1]).addReg(ArgReg+1)
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.addReg(ArgReg+1);
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} else {
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BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
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@ -1254,17 +1255,15 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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}
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ArgOffset += 4; // 8 byte entry, not 4.
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if (GPR_remaining > 0) {
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GPR_remaining -= 1; // uses up 2 GPRs
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GPR_idx += 1;
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}
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GPR_remaining -= 1; // uses up 2 GPRs
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GPR_idx += 1;
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break;
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case cFP:
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ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
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if (Args[i].Ty == Type::FloatTy) {
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// Reg or stack?
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if (FPR_remaining > 0) {
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BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
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BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
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FPR_remaining--;
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FPR_idx++;
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} else {
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@ -1275,7 +1274,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
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// Reg or stack?
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if (FPR_remaining > 0) {
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BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
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BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
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FPR_remaining--;
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FPR_idx++;
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} else {
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@ -1284,20 +1283,16 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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}
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ArgOffset += 4; // 8 byte entry, not 4.
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if (GPR_remaining > 0) {
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GPR_remaining--; // uses up 2 GPRs
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GPR_idx++;
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}
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GPR_remaining--; // uses up 2 GPRs
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GPR_idx++;
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}
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break;
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default: assert(0 && "Unknown class!");
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}
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ArgOffset += 4;
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if (GPR_remaining > 0) {
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GPR_remaining--; // uses up 2 GPRs
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GPR_idx++;
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}
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GPR_remaining--;
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GPR_idx++;
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}
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} else {
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BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
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@ -1863,7 +1858,7 @@ void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned AHBLplusOverflowReg;
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if (OverflowReg) {
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AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
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BuildMI(BB, IP, PPC32::ADD, 2,
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AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
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} else {
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AHBLplusOverflowReg = AHBLReg;
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@ -1873,10 +1868,10 @@ void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg)
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.addReg(AHBLplusOverflowReg);
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} else {
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unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
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unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
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doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
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BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
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BuildMI(BB, IP, PPC32::ADD, 2,
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DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
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}
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return;
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@ -1886,23 +1881,23 @@ void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned Op1Reg = getReg(Op1, &BB, IP);
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// Multiply the two low parts... capturing carry into EDX
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BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL
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// Multiply the two low parts...
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BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
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unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL >> 32
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BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg);
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unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
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unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
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unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
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AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
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BuildMI(BB, IP, PPC32::ADD, 2, AHBLplusOverflowReg).addReg(AHBLReg)
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.addReg(OverflowReg);
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unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
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BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
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BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
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BuildMI(BB, IP, PPC32::ADD, 2,
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DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
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}
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@ -2134,8 +2129,10 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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.addReg(ShiftAmountReg);
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} else {
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if (isSigned) {
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// FIXME: Unimplmented
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// FIXME: Unimplemented
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// Page C-3 of the PowerPC 32bit Programming Environments Manual
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std::cerr << "Unimplemented: signed right shift\n";
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abort();
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} else {
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BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
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.addImm(32);
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@ -2613,7 +2610,13 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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gep_type_end(Src->getType(), IdxBegin, IdxEnd));
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// Keep emitting instructions until we consume the entire GEP instruction.
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while (!GEPTypes.empty()) {
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while (!GEPOps.empty()) {
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if (GEPTypes.empty()) {
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// Load the base pointer into a register.
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unsigned Reg = getReg(Src, MBB, IP);
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BuildMI(*MBB, IP, PPC32::OR, 2, TargetReg).addReg(Reg).addReg(Reg);
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break; // we are now done
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}
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// It's an array or pointer access: [ArraySize x ElementType].
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const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
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Value *idx = GEPOps.back();
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@ -2621,7 +2624,7 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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GEPTypes.pop_back();
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// Many GEP instructions use a [cast (int/uint) to LongTy] as their
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// operand on X86. Handle this case directly now...
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// operand. Handle this case directly now...
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if (CastInst *CI = dyn_cast<CastInst>(idx))
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if (CI->getOperand(0)->getType() == Type::IntTy ||
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CI->getOperand(0)->getType() == Type::UIntTy)
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@ -2633,7 +2636,9 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
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const Type *ElTy = SqTy->getElementType();
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unsigned elementSize = TD.getTypeSize(ElTy);
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if (elementSize == 1) {
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if (idx == Constant::getNullValue(idx->getType())) {
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// GEP with idx 0 is a no-op
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} else if (elementSize == 1) {
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// If the element size is 1, we don't have to multiply, just add
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unsigned idxReg = getReg(idx, MBB, IP);
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unsigned Reg = makeAnotherReg(Type::UIntTy);
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@ -366,16 +366,11 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
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return Reg;
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} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
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// GV is located at PC + distance
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unsigned LRsave = makeAnotherReg(Type::IntTy);
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unsigned CurPC = makeAnotherReg(Type::IntTy);
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unsigned Reg1 = makeAnotherReg(V->getType());
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unsigned Reg2 = makeAnotherReg(V->getType());
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// Save the old LR
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BuildMI(*MBB, IPt, PPC32::MFLR, 0, LRsave);
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// Move PC to destination reg
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BuildMI(*MBB, IPt, PPC32::MovePCtoLR, 0, CurPC);
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// Restore the old LR
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BuildMI(*MBB, IPt, PPC32::MTLR, 1).addReg(LRsave);
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// Move value at PC + distance into return reg
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BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
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.addGlobalAddress(GV);
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@ -1202,10 +1197,16 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Arguments go on the stack in reverse order, as specified by the ABI.
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unsigned ArgOffset = 0;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned GPR_idx = 3;
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unsigned FPR_idx = 1;
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int GPR_remaining = 8, FPR_remaining = 8;
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unsigned GPR[] = {
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PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
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PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
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};
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unsigned FPR[] = {
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PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4,
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PPC32::F5, PPC32::F6, PPC32::F7, PPC32::F8
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};
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unsigned GPR_idx = 0, FPR_idx = 0;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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unsigned ArgReg;
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@ -1218,7 +1219,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Reg or stack?
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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} else {
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BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
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@ -1230,7 +1231,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Reg or stack?
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if (GPR_remaining > 0) {
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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} else {
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BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
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@ -1242,9 +1243,9 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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// Reg or stack?
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if (GPR_remaining > 1) {
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
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.addReg(ArgReg);
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BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx + 1).addReg(ArgReg+1)
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BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx + 1]).addReg(ArgReg+1)
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.addReg(ArgReg+1);
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} else {
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BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
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@ -1254,17 +1255,15 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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}
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ArgOffset += 4; // 8 byte entry, not 4.
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if (GPR_remaining > 0) {
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GPR_remaining -= 1; // uses up 2 GPRs
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GPR_idx += 1;
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}
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GPR_remaining -= 1; // uses up 2 GPRs
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GPR_idx += 1;
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break;
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case cFP:
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ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
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if (Args[i].Ty == Type::FloatTy) {
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// Reg or stack?
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if (FPR_remaining > 0) {
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BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
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BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
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FPR_remaining--;
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FPR_idx++;
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} else {
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@ -1275,7 +1274,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
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// Reg or stack?
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if (FPR_remaining > 0) {
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BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
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BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
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FPR_remaining--;
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FPR_idx++;
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} else {
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@ -1284,20 +1283,16 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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}
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ArgOffset += 4; // 8 byte entry, not 4.
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if (GPR_remaining > 0) {
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GPR_remaining--; // uses up 2 GPRs
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GPR_idx++;
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}
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GPR_remaining--; // uses up 2 GPRs
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GPR_idx++;
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}
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break;
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default: assert(0 && "Unknown class!");
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}
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ArgOffset += 4;
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if (GPR_remaining > 0) {
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GPR_remaining--; // uses up 2 GPRs
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GPR_idx++;
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}
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GPR_remaining--;
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GPR_idx++;
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}
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} else {
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BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
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@ -1863,7 +1858,7 @@ void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned AHBLplusOverflowReg;
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if (OverflowReg) {
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AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
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BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
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BuildMI(BB, IP, PPC32::ADD, 2,
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AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
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} else {
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AHBLplusOverflowReg = AHBLReg;
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@ -1873,10 +1868,10 @@ void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg)
|
||||
.addReg(AHBLplusOverflowReg);
|
||||
} else {
|
||||
unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
|
||||
unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
|
||||
doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
|
||||
|
||||
BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
|
||||
BuildMI(BB, IP, PPC32::ADD, 2,
|
||||
DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
|
||||
}
|
||||
return;
|
||||
@ -1886,23 +1881,23 @@ void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
|
||||
|
||||
unsigned Op1Reg = getReg(Op1, &BB, IP);
|
||||
|
||||
// Multiply the two low parts... capturing carry into EDX
|
||||
BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL
|
||||
// Multiply the two low parts...
|
||||
BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
|
||||
|
||||
unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
|
||||
BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL >> 32
|
||||
BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg);
|
||||
|
||||
unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
|
||||
unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
|
||||
BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
|
||||
|
||||
unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
|
||||
BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
|
||||
AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
|
||||
BuildMI(BB, IP, PPC32::ADD, 2, AHBLplusOverflowReg).addReg(AHBLReg)
|
||||
.addReg(OverflowReg);
|
||||
|
||||
unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
|
||||
BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
|
||||
|
||||
BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
|
||||
BuildMI(BB, IP, PPC32::ADD, 2,
|
||||
DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
|
||||
}
|
||||
|
||||
@ -2134,8 +2129,10 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
|
||||
.addReg(ShiftAmountReg);
|
||||
} else {
|
||||
if (isSigned) {
|
||||
// FIXME: Unimplmented
|
||||
// FIXME: Unimplemented
|
||||
// Page C-3 of the PowerPC 32bit Programming Environments Manual
|
||||
std::cerr << "Unimplemented: signed right shift\n";
|
||||
abort();
|
||||
} else {
|
||||
BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
|
||||
.addImm(32);
|
||||
@ -2613,7 +2610,13 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
gep_type_end(Src->getType(), IdxBegin, IdxEnd));
|
||||
|
||||
// Keep emitting instructions until we consume the entire GEP instruction.
|
||||
while (!GEPTypes.empty()) {
|
||||
while (!GEPOps.empty()) {
|
||||
if (GEPTypes.empty()) {
|
||||
// Load the base pointer into a register.
|
||||
unsigned Reg = getReg(Src, MBB, IP);
|
||||
BuildMI(*MBB, IP, PPC32::OR, 2, TargetReg).addReg(Reg).addReg(Reg);
|
||||
break; // we are now done
|
||||
}
|
||||
// It's an array or pointer access: [ArraySize x ElementType].
|
||||
const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
|
||||
Value *idx = GEPOps.back();
|
||||
@ -2621,7 +2624,7 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
GEPTypes.pop_back();
|
||||
|
||||
// Many GEP instructions use a [cast (int/uint) to LongTy] as their
|
||||
// operand on X86. Handle this case directly now...
|
||||
// operand. Handle this case directly now...
|
||||
if (CastInst *CI = dyn_cast<CastInst>(idx))
|
||||
if (CI->getOperand(0)->getType() == Type::IntTy ||
|
||||
CI->getOperand(0)->getType() == Type::UIntTy)
|
||||
@ -2633,7 +2636,9 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
const Type *ElTy = SqTy->getElementType();
|
||||
unsigned elementSize = TD.getTypeSize(ElTy);
|
||||
|
||||
if (elementSize == 1) {
|
||||
if (idx == Constant::getNullValue(idx->getType())) {
|
||||
// GEP with idx 0 is a no-op
|
||||
} else if (elementSize == 1) {
|
||||
// If the element size is 1, we don't have to multiply, just add
|
||||
unsigned idxReg = getReg(idx, MBB, IP);
|
||||
unsigned Reg = makeAnotherReg(Type::UIntTy);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user