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[ARM GlobalISel] Remove C++ code for G_CONSTANT

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Get rid of the handwritten instruction selector code for handling
G_CONSTANT. This code wasn't checking all the preconditions correctly
anyway, so it's better to leave it to TableGen, which can handle at
least some cases correctly (e.g. MOVi, MOVi16, folding into binary
operations). Also add tests to cover those cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318146 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus 2017-11-14 11:20:32 +00:00
parent a466503cd3
commit 155567c8fe
3 changed files with 65 additions and 26 deletions
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22
lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -796,28 +796,6 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
I.setDesc(TII.get(ARM::ADDri));
MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
break;
case G_CONSTANT: {
unsigned Reg = I.getOperand(0).getReg();
if (!validReg(MRI, Reg, 32, ARM::GPRRegBankID))
return false;
I.setDesc(TII.get(ARM::MOVi));
MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
auto &Val = I.getOperand(1);
if (Val.isCImm()) {
if (Val.getCImm()->getBitWidth() > 32)
return false;
Val.ChangeToImmediate(Val.getCImm()->getZExtValue());
}
if (!Val.isImm()) {
return false;
}
break;
}
case G_GLOBAL_VALUE:
return selectGlobal(MIB, MRI);
case G_STORE:

61
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -8,6 +8,8 @@
define void @test_trunc_and_anyext_s16() { ret void }
define void @test_add_s32() { ret void }
define void @test_add_fold_imm_s32() { ret void }
define void @test_add_no_fold_imm_s32() #3 { ret void }
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
@ -51,6 +53,7 @@
attributes #0 = { "target-features"="+vfp2,-neonfp" }
attributes #1 = { "target-features"="+v6" }
attributes #2 = { "target-features"="+hwdiv-arm" }
attributes #3 = { "target-features"="+v6t2" }
...
---
name: test_trunc_and_zext_s1
@ -264,6 +267,64 @@ body: |
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_add_fold_imm_s32
# CHECK-LABEL: name: test_add_fold_imm_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 255
%2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_add_no_fold_imm_s32
# CHECK-LABEL: name: test_add_no_fold_imm_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 65535
; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, _
%2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: true

8
test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -mtriple arm-gnueabi -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
; RUN: llc -mtriple arm-gnueabi -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
; RUN: llc -mtriple arm-gnu -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
; RUN: llc -mtriple arm-gnu -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
; RUN: llc -mtriple arm-gnueabi -mattr=+v6t2,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
; RUN: llc -mtriple arm-gnueabi -mattr=+v6t2,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
; RUN: llc -mtriple arm-gnu -mattr=+v6t2,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
; RUN: llc -mtriple arm-gnu -mattr=+v6t2,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) {
; CHECK-LABEL: test_sdiv_i32: