From 15c94d08ab2be2e3d00de4edbfc7adde6545a7db Mon Sep 17 00:00:00 2001
From: Sanjiv Gupta <sanjiv.gupta@microchip.com>
Date: Sun, 18 Jan 2009 18:25:27 +0000
Subject: [PATCH] Few targets like PIC16 wants libcall generation for illegal
 type i16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62467 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/RuntimeLibcalls.h           |  4 ++++
 .../SelectionDAG/LegalizeIntegerTypes.cpp        | 16 ++++++++++++----
 lib/CodeGen/SelectionDAG/TargetLowering.cpp      |  4 ++++
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/include/llvm/CodeGen/RuntimeLibcalls.h b/include/llvm/CodeGen/RuntimeLibcalls.h
index e134e788ed0..417f8d3f749 100644
--- a/include/llvm/CodeGen/RuntimeLibcalls.h
+++ b/include/llvm/CodeGen/RuntimeLibcalls.h
@@ -29,15 +29,19 @@ namespace RTLIB {
   ///
   enum Libcall {
     // Integer
+    SHL_I16,
     SHL_I32,
     SHL_I64,
     SHL_I128,
+    SRL_I16,
     SRL_I32,
     SRL_I64,
     SRL_I128,
+    SRA_I16,
     SRA_I32,
     SRA_I64,
     SRA_I128,
+    MUL_I16,
     MUL_I32,
     MUL_I64,
     MUL_I128,
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 45df410ae2c..d84cd62b68e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1586,7 +1586,9 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
 
   // If nothing else, we can make a libcall.
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  if (VT == MVT::i32)
+  if (VT == MVT::i16)
+    LC = RTLIB::MUL_I16;
+  else if (VT == MVT::i32)
     LC = RTLIB::MUL_I32;
   else if (VT == MVT::i64)
     LC = RTLIB::MUL_I64;
@@ -1662,7 +1664,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
   bool isSigned;
   if (N->getOpcode() == ISD::SHL) {
     isSigned = false; /*sign irrelevant*/
-    if (VT == MVT::i32)
+    if (VT == MVT::i16)
+      LC = RTLIB::SHL_I16;
+    else if (VT == MVT::i32)
       LC = RTLIB::SHL_I32;
     else if (VT == MVT::i64)
       LC = RTLIB::SHL_I64;
@@ -1670,7 +1674,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
       LC = RTLIB::SHL_I128;
   } else if (N->getOpcode() == ISD::SRL) {
     isSigned = false;
-    if (VT == MVT::i32)
+    if (VT == MVT::i16)
+      LC = RTLIB::SRL_I16;
+    else if (VT == MVT::i32)
       LC = RTLIB::SRL_I32;
     else if (VT == MVT::i64)
       LC = RTLIB::SRL_I64;
@@ -1679,7 +1685,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
   } else {
     assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
     isSigned = true;
-    if (VT == MVT::i32)
+    if (VT == MVT::i16)
+      LC = RTLIB::SRA_I16;
+    else if (VT == MVT::i32)
       LC = RTLIB::SRA_I32;
     else if (VT == MVT::i64)
       LC = RTLIB::SRA_I64;
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 41b43d91671..364a12177ff 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -29,15 +29,19 @@ using namespace llvm;
 /// InitLibcallNames - Set default libcall names.
 ///
 static void InitLibcallNames(const char **Names) {
+  Names[RTLIB::SHL_I16] = "__ashli16";
   Names[RTLIB::SHL_I32] = "__ashlsi3";
   Names[RTLIB::SHL_I64] = "__ashldi3";
   Names[RTLIB::SHL_I128] = "__ashlti3";
+  Names[RTLIB::SRL_I16] = "__lshri16";
   Names[RTLIB::SRL_I32] = "__lshrsi3";
   Names[RTLIB::SRL_I64] = "__lshrdi3";
   Names[RTLIB::SRL_I128] = "__lshrti3";
+  Names[RTLIB::SRA_I16] = "__ashri16";
   Names[RTLIB::SRA_I32] = "__ashrsi3";
   Names[RTLIB::SRA_I64] = "__ashrdi3";
   Names[RTLIB::SRA_I128] = "__ashrti3";
+  Names[RTLIB::MUL_I16] = "__muli16";
   Names[RTLIB::MUL_I32] = "__mulsi3";
   Names[RTLIB::MUL_I64] = "__muldi3";
   Names[RTLIB::MUL_I128] = "__multi3";