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R600/SI: Minor cleanup of function

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-10-13 15:47:59 +00:00
parent ec8aeb0bc1
commit 162415e8db
1 changed files with 11 additions and 9 deletions
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20
lib/Target/R600/SIInstrInfo.cpp
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@ -1211,26 +1211,28 @@ bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
MachineBasicBlock::iterator I = MI;
MachineBasicBlock *MBB = MI->getParent();
MachineOperand &MO = MI->getOperand(OpIdx);
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
const TargetRegisterClass *RC = RI.getRegClass(RCID);
unsigned Opcode = AMDGPU::V_MOV_B32_e32;
if (MO.isReg()) {
if (MO.isReg())
Opcode = AMDGPU::COPY;
} else if (RI.isSGPRClass(RC)) {
else if (RI.isSGPRClass(RC))
Opcode = AMDGPU::S_MOV_B32;
}
const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
VRC = &AMDGPU::VReg_64RegClass;
} else {
else
VRC = &AMDGPU::VReg_32RegClass;
}
unsigned Reg = MRI.createVirtualRegister(VRC);
BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
Reg).addOperand(MO);
DebugLoc DL = MBB->findDebugLoc(I);
BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
.addOperand(MO);
MO.ChangeToRegister(Reg, false);
}