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Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
does not have a legal type. The legalizer does not know how to handle those nodes. Radar 7854640. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2167,6 +2167,13 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
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static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
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SDValue Op = N->getOperand(0);
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// Do not create a VMOVDRR or VMOVRRD node if the operand type is not
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// legal. The legalizer won't know what to do with that.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (!TLI.isTypeLegal(Op.getValueType()))
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return SDValue();
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DebugLoc dl = N->getDebugLoc();
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if (N->getValueType(0) == MVT::f64) {
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// Turn i64->f64 into VMOVDRR.
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@ -3114,21 +3121,21 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) {
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SDValue Res;
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switch (N->getOpcode()) {
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default:
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llvm_unreachable("Don't know how to custom expand this!");
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return;
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break;
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case ISD::BIT_CONVERT:
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Results.push_back(ExpandBIT_CONVERT(N, DAG));
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return;
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Res = ExpandBIT_CONVERT(N, DAG);
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break;
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case ISD::SRL:
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case ISD::SRA: {
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SDValue Res = LowerShift(N, DAG, Subtarget);
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if (Res.getNode())
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Results.push_back(Res);
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return;
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}
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case ISD::SRA:
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Res = LowerShift(N, DAG, Subtarget);
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break;
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}
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if (Res.getNode())
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Results.push_back(Res);
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}
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//===----------------------------------------------------------------------===//
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16
test/CodeGen/ARM/2010-04-14-SplitVector.ll
Normal file
16
test/CodeGen/ARM/2010-04-14-SplitVector.ll
Normal file
@ -0,0 +1,16 @@
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; RUN: llc < %s -march=arm -mcpu=arm1136jf-s
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; Radar 7854640
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define arm_apcscc void @test() nounwind {
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bb:
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br i1 undef, label %bb9, label %bb10
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bb9:
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%tmp63 = bitcast <4 x float> zeroinitializer to i128
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%tmp64 = trunc i128 %tmp63 to i32
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br label %bb10
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bb10:
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%0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ]
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ret void
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}
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