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[AArch64] AsmParser should be case insensitive about accepting vector register names.

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Differential Revision: http://reviews.llvm.org/D10320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ranjeet Singh 2015-06-08 21:32:16 +00:00
parent 4332f869bf
commit 1666977cd0
2 changed files with 9 additions and 1 deletions
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2
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -1764,7 +1764,7 @@ static unsigned MatchRegisterName(StringRef Name);
/// }
static unsigned matchVectorRegName(StringRef Name) {
return StringSwitch<unsigned>(Name)
return StringSwitch<unsigned>(Name.lower())
.Case("v0", AArch64::Q0)
.Case("v1", AArch64::Q1)
.Case("v2", AArch64::Q2)

8
test/MC/AArch64/case-insen-reg-names.s Normal file
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@ -0,0 +1,8 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
fadd v0.2d, v5.2d, v6.2d
fadd V0.2d, V5.2d, V6.2d
fadd v0.2d, V5.2d, v6.2d
// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e]
// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e]
// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e]