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https://github.com/RPCS3/llvm.git
synced 2024-12-25 13:35:10 +00:00
yea, lowering this stuff will basically work
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25549 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
8c6f1ee5aa
commit
167bc6ee7a
@ -20,6 +20,7 @@
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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@ -68,6 +69,12 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
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if (EnableAlphaLSMark) {
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setOperationAction(ISD::LOAD, MVT::i64, Custom);
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setOperationAction(ISD::LOAD, MVT::f64, Custom);
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setOperationAction(ISD::LOAD, MVT::f32, Custom);
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}
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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@ -145,6 +152,12 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case AlphaISD::RelLit: return "Alpha::RelLit";
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case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
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case AlphaISD::DivCall: return "Alpha::DivCall";
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case AlphaISD::LDQ_: return "Alpha::LDQ_";
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case AlphaISD::LDT_: return "Alpha::LDT_";
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case AlphaISD::LDS_: return "Alpha::LDS_";
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case AlphaISD::LDL_: return "Alpha::LDL_";
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case AlphaISD::LDWU_: return "Alpha::LDWU_";
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case AlphaISD::LDBU_: return "Alpha::LDBU_";
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}
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}
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@ -396,7 +409,6 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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return std::make_pair(Result, Update);
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}
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SDOperand AlphaTargetLowering::
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LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
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Value *DestV, SelectionDAG &DAG) {
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@ -425,6 +437,53 @@ void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
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}
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static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
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{
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fun = type = offset = 0;
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if (v == NULL) {
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type = 0;
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} else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
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type = 1;
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const Module* M = GV->getParent();
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for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
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++offset;
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} else if (const Argument* Arg = dyn_cast<Argument>(v)) {
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type = 2;
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const Function* F = Arg->getParent();
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const Module* M = F->getParent();
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for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
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++fun;
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for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
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++offset;
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} else if (const Instruction* I = dyn_cast<Instruction>(v)) {
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assert(dyn_cast<PointerType>(I->getType()));
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type = 3;
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const BasicBlock* bb = I->getParent();
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const Function* F = bb->getParent();
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const Module* M = F->getParent();
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for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
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++fun;
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for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
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offset += ii->size();
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for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
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++offset;
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} else if (const Constant* C = dyn_cast<Constant>(v)) {
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//Don't know how to look these up yet
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type = 0;
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} else {
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assert(0 && "Error in value marking");
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}
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//type = 4: register spilling
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//type = 5: global address loading or constant loading
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}
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static int getUID()
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{
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static int id = 0;
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return ++id;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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@ -516,6 +575,53 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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break;
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case ISD::LOAD:
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case ISD::SEXTLOAD:
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case ISD::ZEXTLOAD:
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{
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SDOperand Chain = Op.getOperand(0);
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SDOperand Address = Op.getOperand(1);
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unsigned Opc;
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unsigned opcode = Op.getOpcode();
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if (opcode == ISD::LOAD)
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switch (Op.Val->getValueType(0)) {
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default: Op.Val->dump(); assert(0 && "Bad load!");
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case MVT::i64: Opc = AlphaISD::LDQ_; break;
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case MVT::f64: Opc = AlphaISD::LDT_; break;
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case MVT::f32: Opc = AlphaISD::LDS_; break;
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}
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else
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switch (cast<VTSDNode>(Op.getOperand(3))->getVT()) {
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default: Op.Val->dump(); assert(0 && "Bad sign extend!");
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case MVT::i32: Opc = AlphaISD::LDL_;
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assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
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case MVT::i16: Opc = AlphaISD::LDWU_;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
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case MVT::i8: Opc = AlphaISD::LDBU_;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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}
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int i, j, k;
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getValueInfo(dyn_cast<SrcValueSDNode>(Op.getOperand(2))->getValue(), i, j, k);
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SDOperand Zero = DAG.getConstant(0, MVT::i64);
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std::vector<MVT::ValueType> VTS;
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VTS.push_back(Op.Val->getValueType(0));
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VTS.push_back(MVT::Other);
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std::vector<SDOperand> ARGS;
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ARGS.push_back(Zero);
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ARGS.push_back(Address);
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ARGS.push_back(DAG.getConstant(i, MVT::i64));
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ARGS.push_back(DAG.getConstant(j, MVT::i64));
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ARGS.push_back(DAG.getConstant(k, MVT::i64));
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ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
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ARGS.push_back(Chain);
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return DAG.getNode(Opc, VTS, ARGS);
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}
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}
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return SDOperand();
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@ -41,6 +41,9 @@ namespace llvm {
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/// DIVCALL - used for special library calls for div and rem
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DivCall,
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///LD, ST
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LDQ_, LDT_, LDS_, LDL_, LDWU_, LDBU_,
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};
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}
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@ -19,15 +19,24 @@ include "AlphaInstrFormats.td"
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def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [
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SDTCisFP<1>, SDTCisFP<0>
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]>;
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def SDTLoadA : SDTypeProfile<1, 6, [ // load
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SDTCisInt<1>, SDTCisPtrTy<2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisInt<5>, SDTCisInt<6>
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]>;
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def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
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def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
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def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
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def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
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def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
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def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
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def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
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def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
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def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
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def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
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def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
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def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
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def Alpha_ldq : SDNode<"AlphaISD::LDQ_", SDTLoadA, [SDNPInFlag]>;
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def Alpha_ldt : SDNode<"AlphaISD::LDT_", SDTLoadA, [SDNPInFlag]>;
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def Alpha_lds : SDNode<"AlphaISD::LDS_", SDTLoadA, [SDNPInFlag]>;
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def Alpha_ldl : SDNode<"AlphaISD::LDL_", SDTLoadA, [SDNPInFlag]>;
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def Alpha_ldwu : SDNode<"AlphaISD::LDWU_", SDTLoadA, [SDNPInFlag]>;
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def Alpha_ldbu : SDNode<"AlphaISD::LDBU_", SDTLoadA, [SDNPInFlag]>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
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@ -114,8 +123,9 @@ def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "; ADJDOWN $amt",
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}
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def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$$$TARGET..ng:\n", []>;
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def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[]>;
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let noResults = 1 in
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def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
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"LSMARKER$$$i$$$j$$$k$$$m:\n",[]>;
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"LSMARKER$$$i$$$j$$$k$$$m:", []>;
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@ -569,6 +579,30 @@ def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
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def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
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(LDQl texternalsym:$ext, GPRC:$RB)>;
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let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB,
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s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in {
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def LDQlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldq $RA,$DISP($RB)",
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[(set GPRC:$RA, (Alpha_ldq imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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}
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let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB,
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s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
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def LDTlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldt $RA,$DISP($RB)",
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[(set F8RC:$RA, (Alpha_ldt imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB,
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s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
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def LDSlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t lds $RA,$DISP($RB)",
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[(set F4RC:$RA, (Alpha_lds imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
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//def LDLlbl : MForm<0x29, 0, 1, "ldl $RA,$DISP($RB)",
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// [(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP), i32))]>;
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//def LDBUlbl : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
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// [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i8))]>;
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//def LDWUlbl : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
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// [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i16))]>;
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def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
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//Basic Floating point ops
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