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Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-11-10 01:28:43 +00:00
parent df78611726
commit 171d09ea53
3 changed files with 50 additions and 34 deletions
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42
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -469,14 +469,15 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
if (Desc.TSFlags & X86II::REX_W)
REX |= 1 << 3;
if (MI.getNumOperands()) {
bool isTwoAddr = II->getNumOperands(Opcode) > 1 &&
unsigned NumOps = II->getNumOperands(Opcode);
if (NumOps) {
bool isTwoAddr = NumOps > 1 &&
II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
bool isTrunc8 = isX86_64TruncToByte(Opcode);
unsigned i = isTwoAddr ? 1 : 0;
for (unsigned e = MI.getNumOperands(); i != e; ++i) {
for (unsigned e = NumOps; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
if (MO.isRegister()) {
unsigned Reg = MO.getReg();
@ -498,7 +499,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= 1 << 2;
i = isTwoAddr ? 2 : 1;
for (unsigned e = MI.getNumOperands(); i != e; ++i) {
for (unsigned e = NumOps; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
if (isX86_64ExtendedReg(MO))
REX |= 1 << 0;
@ -510,7 +511,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
REX |= 1 << 2;
unsigned Bit = 0;
i = isTwoAddr ? 2 : 1;
for (; i != MI.getNumOperands(); ++i) {
for (; i != NumOps; ++i) {
const MachineOperand& MO = MI.getOperand(i);
if (MO.isRegister()) {
if (isX86_64ExtendedReg(MO))
@ -527,7 +528,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
case X86II::MRMDestMem: {
unsigned e = isTwoAddr ? 5 : 4;
i = isTwoAddr ? 1 : 0;
if (MI.getNumOperands() > e && isX86_64ExtendedReg(MI.getOperand(e)))
if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
REX |= 1 << 2;
unsigned Bit = 0;
for (; i != e; ++i) {
@ -544,7 +545,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= 1 << 0;
i = isTwoAddr ? 2 : 1;
for (unsigned e = MI.getNumOperands(); i != e; ++i) {
for (unsigned e = NumOps; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
if (isX86_64ExtendedReg(MO))
REX |= 1 << 2;
@ -607,8 +608,9 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
MCE.emitByte(0x0F);
// If this is a two-address instruction, skip one of the register operands.
unsigned NumOps = II->getNumOperands(Opcode);
unsigned CurOp = 0;
if (II->getNumOperands(Opcode) > 1 &&
if (NumOps > 1 &&
II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1)
CurOp++;
@ -637,12 +639,12 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
break;
}
#endif
CurOp = MI.getNumOperands();
CurOp = NumOps;
break;
case X86II::RawFrm:
MCE.emitByte(BaseOpcode);
if (CurOp != MI.getNumOperands()) {
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
if (MO.isMachineBasicBlock()) {
emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
@ -663,7 +665,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
case X86II::AddRegFrm:
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
if (CurOp != MI.getNumOperands()) {
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
if (MO1.isGlobalAddress()) {
assert(sizeOfImm(Desc) == TD->getPointerSize() &&
@ -688,7 +690,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
getX86RegNum(MI.getOperand(CurOp+1).getReg()));
CurOp += 2;
if (CurOp != MI.getNumOperands())
if (CurOp != NumOps)
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
break;
}
@ -696,7 +698,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
CurOp += 5;
if (CurOp != MI.getNumOperands())
if (CurOp != NumOps)
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
break;
}
@ -706,18 +708,18 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
getX86RegNum(MI.getOperand(CurOp).getReg()));
CurOp += 2;
if (CurOp != MI.getNumOperands())
if (CurOp != NumOps)
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
break;
case X86II::MRMSrcMem: {
unsigned PCAdj = (CurOp+5 != MI.getNumOperands()) ? sizeOfImm(Desc) : 0;
unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
PCAdj);
CurOp += 5;
if (CurOp != MI.getNumOperands())
if (CurOp != NumOps)
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
break;
}
@ -730,7 +732,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
(Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
if (CurOp != MI.getNumOperands() && MI.getOperand(CurOp).isImmediate())
if (CurOp != NumOps && MI.getOperand(CurOp).isImmediate())
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
break;
@ -738,7 +740,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
case X86II::MRM2m: case X86II::MRM3m:
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m: {
unsigned PCAdj = (CurOp+4 != MI.getNumOperands()) ?
unsigned PCAdj = (CurOp+4 != NumOps) ?
(MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
MCE.emitByte(BaseOpcode);
@ -746,7 +748,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
PCAdj);
CurOp += 4;
if (CurOp != MI.getNumOperands()) {
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
if (MO.isImmediate())
emitConstant(MO.getImm(), sizeOfImm(Desc));
@ -770,5 +772,5 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
}
assert((Desc.Flags & M_VARIABLE_OPS) != 0 ||
CurOp == MI.getNumOperands() && "Unknown encoding!");
CurOp == NumOps && "Unknown encoding!");
}

22
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -500,11 +500,14 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
MachineFunction *MF = MI->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
unsigned NumOps = TII.getNumOperands(MI->getOpcode());
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
// Is this the last use of the source register?
unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
// FISTP64m is strange because there isn't a non-popping versions.
@ -524,7 +527,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
}
// Convert from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand
MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
if (MI->getOpcode() == X86::FISTP64m ||
@ -549,7 +552,10 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
assert(MI->getNumOperands() >= 2 && "FPRW instructions must have 2 ops!!");
MachineFunction *MF = MI->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
unsigned NumOps = TII.getNumOperands(MI->getOpcode());
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
unsigned Reg = getFPReg(MI->getOperand(1));
@ -625,7 +631,9 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getNumOperands();
MachineFunction *MF = MI->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
unsigned NumOperands = TII.getNumOperands(MI->getOpcode());
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@ -722,7 +730,9 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getNumOperands();
MachineFunction *MF = MI->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
unsigned NumOperands = TII.getNumOperands(MI->getOpcode());
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));

20
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -161,8 +161,9 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
unsigned NumOps = MI->getNumOperands()-2;
MachineInstr *MI,
const TargetInstrInfo &TII) {
unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
// Create the base instruction with the memory operand as the first part.
MachineInstrBuilder MIB = addFrameReference(BuildMI(Opcode, 4+NumOps),
FrameIndex);
@ -185,7 +186,8 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
}
static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
unsigned FrameIndex, MachineInstr *MI) {
unsigned FrameIndex, MachineInstr *MI,
const TargetInstrInfo &TII) {
MachineInstrBuilder MIB = BuildMI(Opcode, MI->getNumOperands()+3);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@ -284,14 +286,16 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
const TableEntry *OpcodeTablePtr = NULL;
unsigned OpcodeTableSize = 0;
bool isTwoAddrFold = false;
bool isTwoAddr = TII.getNumOperands(MI->getOpcode()) > 1 &&
unsigned NumOps = TII.getNumOperands(MI->getOpcode());
bool isTwoAddr = NumOps > 1 &&
TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// replacing the *two* registers with the memory location.
if (isTwoAddr && MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() &&
MI->getOperand(1).isReg() && i < 2 &&
if (isTwoAddr && NumOps >= 2 && i < 2 &&
MI->getOperand(0).isReg() &&
MI->getOperand(1).isReg() &&
MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
static const TableEntry OpcodeTable[] = {
{ X86::ADC32ri, X86::ADC32mi },
@ -823,9 +827,9 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
fromOpcode)) {
if (isTwoAddrFold)
return FuseTwoAddrInst(Entry->to, FrameIndex, MI);
return FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
return FuseInst(Entry->to, i, FrameIndex, MI);
return FuseInst(Entry->to, i, FrameIndex, MI, TII);
}
}