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asmprint pseudo instrs

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24742 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-16 07:13:26 +00:00
parent d4f2ab5e00
commit 17392e026a
4 changed files with 20 additions and 48 deletions
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17
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -422,19 +422,6 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
if (CloseParen) O << ")"; if (CloseParen) O << ")";
} }
static bool isPseudoInstruction (const MachineInstr *MI) {
switch (MI->getOpcode ()) {
case V8::PHI:
case V8::ADJCALLSTACKUP:
case V8::ADJCALLSTACKDOWN:
case V8::IMPLICIT_USE:
case V8::IMPLICIT_DEF:
return true;
default:
return false;
}
}
/// printBaseOffsetPair - Print two consecutive operands of MI, starting at #i, /// printBaseOffsetPair - Print two consecutive operands of MI, starting at #i,
/// which form a base + offset pair (which may have brackets around it, if /// which form a base + offset pair (which may have brackets around it, if
/// brackets is true, or may be in the form base - constant, if offset is a /// brackets is true, or may be in the form base - constant, if offset is a
@ -467,10 +454,6 @@ void SparcV8AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetInstrDescriptor &Desc = TII.get(Opcode); const TargetInstrDescriptor &Desc = TII.get(Opcode);
// If it's a pseudo-instruction, comment it out.
if (isPseudoInstruction (MI))
O << "! ";
O << Desc.Name << " "; O << Desc.Name << " ";
// print non-immediate, non-register-def operands // print non-immediate, non-register-def operands

17
lib/Target/Sparc/SparcInstrInfo.td
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@ -35,16 +35,19 @@ include "SparcV8InstrFormats.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions. // Pseudo instructions.
class PseudoInstV8<string nm, dag ops> : InstV8 { class PseudoInstV8<string asmstr, dag ops> : InstV8 {
let Name = nm; let AsmString = asmstr;
dag OperandList = ops; dag OperandList = ops;
} }
def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN", (ops variable_ops)>; def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP", (ops variable_ops)>; (ops i32imm:$amt)>;
def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE", (ops variable_ops)>; def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF", (ops variable_ops)>; (ops i32imm:$amt)>;
def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
(ops IntRegs:$dst)>;
def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
// Section A.3 - Synthetic Instructions, p. 85 // Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL: // special cases of JMPL:

17
lib/Target/SparcV8/SparcV8AsmPrinter.cpp
View File

@ -422,19 +422,6 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
if (CloseParen) O << ")"; if (CloseParen) O << ")";
} }
static bool isPseudoInstruction (const MachineInstr *MI) {
switch (MI->getOpcode ()) {
case V8::PHI:
case V8::ADJCALLSTACKUP:
case V8::ADJCALLSTACKDOWN:
case V8::IMPLICIT_USE:
case V8::IMPLICIT_DEF:
return true;
default:
return false;
}
}
/// printBaseOffsetPair - Print two consecutive operands of MI, starting at #i, /// printBaseOffsetPair - Print two consecutive operands of MI, starting at #i,
/// which form a base + offset pair (which may have brackets around it, if /// which form a base + offset pair (which may have brackets around it, if
/// brackets is true, or may be in the form base - constant, if offset is a /// brackets is true, or may be in the form base - constant, if offset is a
@ -467,10 +454,6 @@ void SparcV8AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetInstrDescriptor &Desc = TII.get(Opcode); const TargetInstrDescriptor &Desc = TII.get(Opcode);
// If it's a pseudo-instruction, comment it out.
if (isPseudoInstruction (MI))
O << "! ";
O << Desc.Name << " "; O << Desc.Name << " ";
// print non-immediate, non-register-def operands // print non-immediate, non-register-def operands

17
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -35,16 +35,19 @@ include "SparcV8InstrFormats.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions. // Pseudo instructions.
class PseudoInstV8<string nm, dag ops> : InstV8 { class PseudoInstV8<string asmstr, dag ops> : InstV8 {
let Name = nm; let AsmString = asmstr;
dag OperandList = ops; dag OperandList = ops;
} }
def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN", (ops variable_ops)>; def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP", (ops variable_ops)>; (ops i32imm:$amt)>;
def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE", (ops variable_ops)>; def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF", (ops variable_ops)>; (ops i32imm:$amt)>;
def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
(ops IntRegs:$dst)>;
def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
// Section A.3 - Synthetic Instructions, p. 85 // Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL: // special cases of JMPL: