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[mips][microMIPS] Implement disassembler support for 16-bit instructions
With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek
parent
a1e1f01699
commit
18700de8fc
@ -700,6 +700,26 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
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return MCDisassembler::Success;
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}
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/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
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/// according to the given endianess.
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static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn,
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bool IsBigEndian) {
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// We want to read exactly 2 Bytes of data.
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if (Bytes.size() < 2) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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if (IsBigEndian) {
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Insn = (Bytes[0] << 8) | Bytes[1];
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} else {
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Insn = (Bytes[1] << 8) | Bytes[0];
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}
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return MCDisassembler::Success;
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}
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/// Read four bytes from the ArrayRef and return 32 bit word sorted
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/// according to the given endianess
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static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
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@ -711,15 +731,19 @@ static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
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return MCDisassembler::Fail;
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}
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// High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
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// always precede the low 16 bits in the instruction stream (that is, they
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// are placed at lower addresses in the instruction stream).
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//
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// microMIPS byte ordering:
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// Big-endian: 0 | 1 | 2 | 3
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// Little-endian: 1 | 0 | 3 | 2
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if (IsBigEndian) {
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// Encoded as a big-endian 32-bit word in the stream.
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Insn =
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(Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
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} else {
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// Encoded as a small-endian 32-bit word in the stream.
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// Little-endian byte ordering:
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// mips32r2: 4 | 3 | 2 | 1
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// microMIPS: 2 | 1 | 4 | 3
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if (IsMicroMips) {
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Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
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(Bytes[1] << 24);
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@ -738,14 +762,25 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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raw_ostream &VStream,
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raw_ostream &CStream) const {
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uint32_t Insn;
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DecodeStatus Result =
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readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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DecodeStatus Result;
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if (IsMicroMips) {
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DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
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Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
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DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 2;
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return Result;
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}
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Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
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this, STI);
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@ -756,6 +791,10 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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return MCDisassembler::Fail;
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}
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Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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if (hasCOP3()) {
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DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
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Result =
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@ -854,7 +893,11 @@ static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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return MCDisassembler::Fail;
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if (RegNo > 7)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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@ -289,10 +289,10 @@ def GPR32 : GPR32Class<[i32]>;
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def DSPR : GPR32Class<[v4i8, v2i16]>;
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def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Callee save
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S0, S1)>;
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S0, S1,
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3)>;
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def GPR64 : RegisterClass<"Mips", [i64], 64, (add
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// Reserved
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@ -321,3 +321,48 @@
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# CHECK: swm32 $16, $17, 8($4)
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0x20 0x44 0xd0 0x08
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# CHECK: addu16 $6, $17, $4
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0x07 0x42
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# CHECK: subu16 $5, $16, $3
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0x06 0xb1
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# CHECK: and16 $16, $2
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0x44 0x82
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# CHECK: not16 $17, $3
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0x44 0x0b
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# CHECK: or16 $16, $4
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0x44 0xc4
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# CHECK: xor16 $17, $5
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0x44 0x4d
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# CHECK: sll16 $3, $16, 5
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0x25 0x8a
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# CHECK: srl16 $4, $17, 6
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0x26 0x1d
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# CHECK: mfhi $9
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0x46 0x09
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# CHECK: mflo $9
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0x46 0x49
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# CHECK: move $25, $1
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0x0f 0x21
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# CHECK: jrc $9
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0x45 0xa9
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# CHECK: jalr $9
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0x45 0xc9
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# CHECK: jalrs16 $9
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0x45 0xe9
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# CHECK: jr16 $9
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0x45 0x89
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@ -321,3 +321,48 @@
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# CHECK: swm32 $16, $17, 8($4)
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0x44 0x20 0x08 0xd0
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# CHECK: addu16 $6, $17, $4
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0x42 0x07
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# CHECK: subu16 $5, $16, $3
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0xb1 0x06
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# CHECK: and16 $16, $2
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0x82 0x44
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# CHECK: not16 $17, $3
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0x0b 0x44
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# CHECK: or16 $16, $4
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0xc4 0x44
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# CHECK: xor16 $17, $5
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0x4d 0x44
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# CHECK: sll16 $3, $16, 5
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0x8a 0x25
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# CHECK: srl16 $4, $17, 6
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0x1d 0x26
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# CHECK: mfhi $9
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0x09 0x46
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# CHECK: mflo $9
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0x49 0x46
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# CHECK: move $25, $1
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0x21 0x0f
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# CHECK: jrc $9
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0xa9 0x45
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# CHECK: jalr $9
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0xc9 0x45
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# CHECK: jalrs16 $9
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0xe9 0x45
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# CHECK: jr16 $9
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0x89 0x45
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